Young-Hun Seo

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

With the growth of wearable devices, such as smart watches and smart glasses, there is an increasing demand for lower power dissipation, to achieve longer battery life with limited battery capacity. Nevertheless, memory bandwidth needs to increase to support high-resolution graphic engines. Since most wearable devices are event driven, they consume a bulk of power in standby mode. Therefore, it is crictical to reduce standby-mode power, as well as improve active-mode power efficiency. However, DRAMs periodic self-refresh, critical for data retention, imposes a lower bound on standby-mode power. This paper presents a 2Gb LPDDR4 SDRAM with 0.15mW standby mode power, which is 66% lower than the standby power for a memory of the same density. The proposed memory also achieves a bandwidth of 3.733Gb/s/pin. To extremely reduce standby mode power, an in-DRAM error-correction-code (ECC) engine is used for self-refresh current reduction. Intensive power gating in deep-power-down (DPD) mode, a temperature controlled internal power generator and an aggressively increased gate length is also used to reduce leakage current. In addition, active-mode power efficiency is improved by using a dual-page-size scheme.