Young-Moon Choi

Integration and Electrical Properties of Carbon Nanotube Array for Interconnect Applications

Carbon nanotube (CNT) vertical integration and electrical properties are presented in full 6-inch wafer for interconnect applications. Series array of 1000 vias made of vertically grown CNTs is obtained with uniform electrical resistances within the wafer. Integration processes are implemented by following sequential steps: bottom electrode and via hole patterning, CNT growth and planarization, and top electrode patterning in a 6-inch wafer. Multiwall carbon nanotubes (MWNTs) are used for interconnection, titanium nitride for the bottom electrode, and aluminum with titanium adhesion layer for the top electrode. We have demonstrated well-defined CNT via series interconnection with 700 nm via diameters within the full wafer. Via resistance of 1.2 kΩ with CNT density of 2.7×1010/cm2is obtained with small resistance variation within the wafer, which also corresponds to 176 kΩ per one MWNT with 10 nm diameters. The possible approaches for further decrease of electrical resistance will be suggested.

Study of the ion-implanted back-surface fields in front-contact front-junction solar cells

We have studied low energy ion-implanted P+ and N+ back surface field (BSF) layers with shallow junctions in front-contact front-junction solar cells for the first time as far as we know. With N+ BSF layer, V<inf>oc</inf> and the efficiency of the solar cells increased on average by 30mV and 1.3%, respectively. N+ BSF layer reduced recombination at the back surface significantly while P+ layer increased it. The higher V<inf>oc</inf> due to the reduced recombination for the N+ BSF and the lower V<inf>oc</inf> due to the increased recombination for the P+ BSF were attributed to the asymmetry in the capture cross-sections of the minority carriers (σ<inf>n</inf> ∼ 100∗σ<inf>p</inf>).

Stack junction approach to overcome silicon single junction limit

We here propose a new scheme to overcome silicon single junction limit efficiency. Interdigitated front contact (IFC) Si cell which is electrically separated by insulating interlayers and stacked with interdigitated back contact (IBC) Ge cell can obtain 5% more efficiency than Si alone. We have fabricated 20.9% top Si / 1.6% bottom Ge stack junction with 22.5% module efficiency. In order to transmit long wavelength photon to the Ge cell and achieve good passivation at the interlayer, SiO2 and SiNx double insulating interlayers were optimized with ion implanted surface field. We eventually hope to reach 26.5% module efficiency with Si / Ge stack junction in the near future.

Interdigitated front contact solar cells fabricated by CMOS process technologies

We have fabricated novel interdigitated front contact structure silicon solar cells by using CMOS process technologies. Shallow emitter junction process using ion implantations and low leakage front contact process using barrier metals were developed. Front local base contact employed self-aligned spacer isolation technologies between emitter and base contacts. And we adjusted these with fine-pattern interdigitated grids to increase energy conversion efficiency. Inverted pyramid texturing, double anti-reflection coating, and trapezoidal metal etch technologies were integrated to increase photo-generated currents. Advanced module fabrication was developed for our cell structure. Integrating these new technologies, we have recorded maximum module efficiency of 20.1% in our laboratory.

High efficiency silicon and Germanium stack junction solar cells

We have fabricated Si/Ge stack junction solar cells in order to overcome silicon single junction limit efficiency. Ge cell can absorb long wavelength photons that cannot be absorbed in Si. Bottom Ge solar cell can theoretically yield additional 5% efficiency to Si top cell. We have fabricated 21.3% top Si / 1.6% bottom Ge stack junction with 22.9% module efficiency. SiO2 and SiNx double insulating interlayers were optimized in order to transmit long wavelength photon to the Ge cell and achieve good passivation at the interlayer. The stack junction will be able to overcome the Si practical efficiency limit of 26% in the near future, and be the candidate for the next generation crystalline Si solar cell.

A novel Dual String NOR (DuSNOR) memory cell technology scalable to the 256 Mbit and 1 Mbit flash memories

We have developed a novel NOR-type flash memory technology named Dual String NOR (DuSNOR). In the DuSNOR cell array, two adjacent cell strings share a source line and up to 128 cell transistors can be attached to a string. This makes the cell size of DuSNOR smaller than NAND, without sacrificing the advantages of the NOR-type cell. Both the program and erase operations utilize the Fowler-Nordheim tunneling. DuSNOR cells with a cell size of 1.60 /spl mu/m/sup 2/ was fabricated using 0.5 /spl mu/m design rules. It was found that the DuSNOR cell has a fast operating speed, reduced overprogram and disturb problems, and excellent endurance characteristics. DuSNOR is a promising technology for high density, high speed, and random-access flash memories with a small cell size, excellent device characteristics and simplicity in the fabrication process.