Younghwi Yang

Read-Preferred SRAM Cell With Write-Assist Circuit Using Back-Gate ETSOI Transistors in 22-nm Technology

The degradation of the read stability and write ability of static random-access memory (SRAM) is becoming a critical problem in deep submicrometer technology. To solve this problem, there are many SRAM cell design options such as preferred cells and assist circuits. In addition, extremely thin silicon-on-insulator (ETSOI) with a buried oxide offers an independent back-gate control. In this paper, previously proposed SRAM back-gate-assist circuit schemes are analyzed. From this, we propose a read-preferred SRAM cell with a write-assist circuit using the back-gate ETSOI. The proposed write-assist circuit minimizes the dynamic power overhead and satisfies a sufficient cell sigma in all cells during the read and write operations.

Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology

Although near-threshold (Vth) operation is an attractive method for energy and performance-constrained applications, it suffers from problems in terms of circuit stability, particularly, for static random access memory (SRAM) cells. This brief proposes a near-Vth 9T SRAM cell implemented in a 22-nm FinFET technology. The read buffer of the proposed cell ensures read stability by decoupling the stored node from the read bit-line and improves read performance using a one-transistor read path. Energy and standby power are reduced by eliminating the sub-Vth leakage current in the read buffer. For accurate sensing yield estimation, a new yield-estimation method is also proposed, which considers the dynamic trip voltage. The proposed SRAM cell can achieve a minimum operating voltage of 0.3 V.

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an average-8T SRAM based on an advanced technology, such as a 22-nm FinFET technology, where the variation in threshold voltage is large, the boosted WL voltage cannot be used, because it degrades the read stability of the SRAM. Thus, a full-swing local BL cannot be achieved, and the gate of the read buffer cannot be driven by the full supply voltage (VDD), resulting in a considerably large read delay. To overcome the above disadvantage, in this paper, a differential SRAM architecture with a full-swing local BL is proposed. In the proposed SRAM architecture, full swing of the local BL is ensured by the use of cross-coupled pMOSs, and the gate of the read buffer is driven by a full VDD, without the need for the boosted WL voltage. Various configurations of the proposed SRAM architecture, which stores multiple bits, are analyzed in terms of the minimum operating voltage and area per bit. The proposed SRAM that stores four bits in one block can achieve a minimum voltage of 0.42 V and a read delay that is 62.6 times lesser than that of the average-8T SRAM based on the 22-nm FinFET technology.

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. This paper proposes an NTV 7T SRAM cell in a 14 nm FinFET technology to eliminate read disturbance by disconnecting the path from the bit-line to the cross-coupled inverter pair using the transmission gate. In the proposed 7T SRAM cell, the half-select issue is resolved, meaning that no write-back operation is required. A folded-column structure is applied to the proposed 7T SRAM cell to reduce the read access time and energy consumption. To reduce the standby power, the proposed 7T SRAM cell uses only a single bit-line for both read and write operations. To achieve proper “1” writing operation with a single bit-line, a two-phase approach is proposed. Compared to the conventional 8T SRAM cell, the proposed 7T SRAM cell improves the read access time, energy, and standby power by 13%, 42%, and 23%, respectively, with a 3% smaller cell area.

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM

An offset-compensated cross-coupled PFET bit-line (BL) conditioning circuit (OC-CPBC) and a selective negative BL write-assist circuit (SNBL-WA) are proposed for high-density FinFET static RAM (SRAM). The word-line (WL) underdrive read-assist and the negative BL write-assist circuits should be used for the stable operation of high-density FinFET SRAM. However, the WL underdrive read-assist circuit degrades the performance, and the negative BL write-assist circuit consumes a large amount of energy. The OC-CPBC enhances BL development during the evaluation phase by applying cross-coupled PFETs whose offset is compensated by precharging each of the two BLs separately through diode-connected cross-coupled PFETs. The SNBL-WA performs a write assist only when a write failure is detected, and this selective write assist reduces the write energy consumption. The simulation results show that the performance and energy consumption are improved by 41% and 48%, respectively, by applying the OC-CPBC and SNBL-WA to SRAM, even with a decrease in area.

SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit

As the semiconductor technology scales down, the read stability and write ability of a static random-access memory (SRAM) cell are degraded because of the increased mismatch among its transistors. Extremely thin silicon-on-insulator is one of the attractive candidates to reduce this mismatch, and it offers an independent back-gate control using a thin buried oxide. The implementation of back-gate control has recently attracted much interest to improve the read stability and write ability. In this paper, we propose a selective cell current (ICELL) boosting scheme (SIB) and an asymmetric back-gate control write-assist (ABC-WA) circuit. SIB enhances the read performance by selectively boosting ICELL of the SRAM cells. ABC-WA enhances the write ability by forward biasing the NMOSs at one side, which improves the write ability with reduction in the dynamic power overhead and without requiring a voltage generator. The proposed SRAM design improves the read performance and energy by 38.6% and 24.9%, respectively.

Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation

A near-threshold voltage (Vth) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super-Vth operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near-Vth region. The recently proposed SRAM bit-cells with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near-Vth region. This paper proposes a read buffer with adjusted the number of fins or Vth to resolve the problems in the near-Vth region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near-Vth region.

Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM

In this paper, we research on fin thickness (T_fin) and fin height (H_fin) effects on read stability and write ability of tri-gate FinFET based SRAM cell. The degree of drain induced barrier lowering changes with T_fin and fin H_fin. This makes threshold voltage (V_th) vary. Thus, T_fin and H_fin also influence the mean and standard deviation of read static noise margin (RSNM) and word-line write trip voltage (WWTV) since V_th variation is a dominant factor determining them. If T_fin increases, the mean of RSNM (μ_RSNM) and the mean of WWTV (μ_WWTV) decreases and increases, respectively, while the standard deviation of RSNM (σ_RSNM) and WWTV (σ_WWTV) are almost not changed. If H_fin increases, the μ_RSNM and μ_WWTV decreases and increases, respectively, while both σ_RSNM and σ_WWTV decrease. However, for a sufficiently small T_fin, the effect of H_fin on μ_RSNM and μ_WWTV becomes negligible.

Comparative study of WL driving method for high-capacity NAND flash memory

In this work, we demonstrated comparative study of the WL driving method in 256-Gb VNAND with 16KB page size. The fixed pulse width (FPW) which uses the fixed WL pulse width with incremental voltage has a large tPROG due to the decreased Vth shift in the later ISPP loop. The incremental pulse width (IPW) which incrementally increases the programming voltage and pulse width overcomes the small Vth shift problem in the later loop. In addition, the optimization methods for FPW and IPW are presented to obtain a small tPROG considering the narrow Vth distribution of NAND cell after programming operation. The comparison of the WL driving methods is performed by HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 16KB page size.

Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region

A figure of merit (FOM) for a CMOS system on chip (SoC) is proposed to correctly assess different CMOS SoCs in the near-threshold voltage (V_th) region, where the supply voltage (V_DD) is slightly higher than V_th. When V_DD is scaled down to near V_th, the drain current becomes greatly sensitive to V_DD or V_th; furthermore, the energy exhibits the same sensitivity as that in the super-V_th region. The conventional FOM, the energy-delay product (EDP), is not applicable in the near-V_th region, because the EDP does not consider the sensitivity difference between the energy and the delay. The procedure for establishing an FOM that can appropriately consider the sensitivity difference by fitting the characteristics of a transistor is first introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super-V_th and near-V_th regions, which verifies that the proposed FOM is appropriate in the near-V_th region, whereas the EDP is not.