Junyoung Ko

Comparative study of WL driving method for high-capacity NAND flash memory

In this work, we demonstrated comparative study of the WL driving method in 256-Gb VNAND with 16KB page size. The fixed pulse width (FPW) which uses the fixed WL pulse width with incremental voltage has a large tPROG due to the decreased Vth shift in the later ISPP loop. The incremental pulse width (IPW) which incrementally increases the programming voltage and pulse width overcomes the small Vth shift problem in the later loop. In addition, the optimization methods for FPW and IPW are presented to obtain a small tPROG considering the narrow Vth distribution of NAND cell after programming operation. The comparison of the WL driving methods is performed by HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 16KB page size.

Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM

Phase-change random access memory (PRAM) is considered to be one of the most promising storage class memory candidates. In this paper, several circuit techniques are introduced to satisfy the target yield and sensing time requirements of an 8-Gb PRAM. First, we propose a temperature-tracking reference current generator to compensate for the variation in data current caused by the change in the resistance of phase-change materials. Second, an adaptive precharge scheme to solve the problem of large parasitic resistances and capacitances of a global bitline is proposed. Finally, we introduce noise compensation schemes to reduce coupling noise. The verification of the proposed circuit techniques is performed by HSPICE simulation using the 0.25- μm model parameters used in peripheral circuit of Samsungs 20 nm PRAM technology. The sensing scheme using temperature tracking reference current generator achieves 9.32σ ( ~ 100%) of read access pass yield in 8-Gb PRAM and 99 ns of the sensing time is achieved using the adaptive precharge scheme and noise compensation schemes.

Response of Single Piles in Marine Deposits to Negative Skin Friction from Long-term Field Monitoring

The behavior of single piles subjected to negative skin friction in soft soil was conducted by analyzing the results from full-scale long-term field measurements and three-dimensional (3D) numerical analyses. A skin friction coefficient (α and β coefficients) of the instrumented piles is back-calculated at different degrees of consolidation (U) of soft marine clay. Back-calculated β-values ranged from 0.15 to 0.35 for clay, and from 0.30 to 0.55 for sand, respectively. In addition, back-calculated α-values ranged from 0.1 to 0.3 for coated pile, and from 0.2 to 0.8 for uncoated pile when undrained shear strength of the soft clay was about 30–60 kPa, respectively. Moreover, this study describes behavior of a pile based on full-coupled 3D finite element (FE) analysis. The appropriate parametric studies needed for verifying the pile-soil interaction with consolidation are presented in this paper. Compared to the results from the measurements, it is shown that the computed results are capable of predicting the pile-soil behavior under consolidation. The major parameters that influence the pile behavior are discussed for different soil-pile conditions.

Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM

Research on phase-change random access memory (PRAM) for multilevel cells (MLCs) has been actively conducted owing to the advantages of PRAM cells, such as large resistance margin and fast read/write access time. However, the resistance drift (R-drift), which increases the resistance of the PRAM cells with time, should be overcome to achieve MLC PRAM operation. In this paper, we introduce sensing methods with R-drift tolerance, namely, drift-resilient cell-state metric and incremental bitline voltage (IBV), and compare these sensing methods in terms of the sensing margin and read access time. In addition, we propose a sensing scheme for IBV (IBVSS) with a half-adaptive threshold reference scheme (H-ATRS) to achieve high-R-drift tolerance in severe R-drift conditions with a small layout area for the reference cell. Verification of the IBVSS with H-ATRS is performed by HSPICE simulation using the 0.25-

WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory

\mu \text{m}

Plugging effect of open-ended piles in sandy soil

model parameters used in the peripheral circuit of Samsung’s 20-nm PRAM technology. From the simulation, we find that the IBVSS with H-ATRS achieves more than 1 V of sensing margin under severe R-drift conditions, which ensures stable read operation in the MLC PRAM with 304 ns of sensing time.

Large deformation FE analysis of driven steel pipe piles with soil plugging

In this work, we compared the WL driving schemes in 512 Gb planar NAND with 32 KB page size. In the conventional WL driving scheme, the rising time of the selected WL voltage is very large because of the large coupling capacitance between the selected and unselected WLs. The WL under-driving scheme (WLUDS) reduces the effect of coupling capacitance by using the 2-phase control of unselected WL voltage. However, when WLUDS is used, the relationship between the rising time and overshoot of the selected WL voltage should be considered in order to achieve the small rising time Therefore, we proposes a novel implementation method for WLUDS that controls the under-driving voltage and under-driving timing by using the decremental step voltage and incremental step time (DSVIST) to enhance the rising time considering the overshoot constraint. The HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 32 KB page size shows that the rising time in the proposed WLUDS with DSVIST is improved to 988 μs compared to 1206 μs in the conventional WL driving scheme.