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Dive into the research topics where Yu-Cheng Fan is active.

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Featured researches published by Yu-Cheng Fan.


IEEE Transactions on Magnetics | 2011

Three-Dimensional Auto-Stereoscopic Image Recording, Mapping and Synthesis System for Multiview 3D Display

Yu-Cheng Fan; Yu-Ting Kung; Bing-Lian Lin

In this paper, we present a 3D auto-stereoscopic image recording, mapping and synthesis system for multiview 3D display. Recursive storage and mapping techniques are addressed to reduce hardware costs for lenticular-based multiview 3D display. Multiview images are synthesized according the recursive storage and mapping rules to present a distinct 3D image. The experimental results prove the proposed scheme has low hardware costs and a realistic 3D feeling.


IEEE Transactions on Magnetics | 2011

Three-Dimensional Depth Map Motion Estimation and Compensation for 3D Video Compression

Yu-Cheng Fan; Shu-Fen Wu; Bing-Lian Lin

In this paper, we propose a new approach to 3D depth map motion estimation and compensation for 3D video compression. 3D video provides realistic vision and will be a feature of future video displays. The many kinds of 3D formats include multiview 3D, single view with a depth map, time division multiple 3D, and so on. 3D video requires huge quantities of data and requires a great deal of storage space to store 3D information. In addition, when 3D video is transmitted, the huge amount of data should be compressed to reduce bandwidth usage. In order to solve this problem, we adopt single view with a depth map 3D format and design a 3D depth map compression scheme for 3D video. We consider depth map motion estimation and compensation to achieve temporal compression of 3D video.


IEEE Transactions on Magnetics | 2014

Predictable Power Saving Memory Controller Circuit Design for Embedded Static Random Access Memory

Yu-Cheng Fan; Chih-Kang Lin; Shih-Ying Chou; Hung-Kuan Liu; Shu-Hsien Wu; Chun-Hung Wang

In this paper, we propose a predictable power saving memory controller circuit (PPSMCC) design for embedded static random access memory. An efficient method is proposed to monitor memory control signal and perform clock gating function that closes idle memory elements to save chip power. At the same time, we dynamically adjust frequency of memory element according to system requirement and achieve low power target. Besides, we propose a strategy to detect signal toggle of memory. When related port is not toggled during the timeslot, we deassert chip enable signal and related port to execute power saving mode for memory. According to the experimental results, the proposed predictable PPSMCC reduces the power consumption efficiency to achieve the low power target.


IEEE Transactions on Magnetics | 2011

Hole-Filling Based Memory Controller of Disparity Modification System for Multiview Three-Dimensional Video

Yu-Cheng Fan; Jung-Ching Chiou; Yan-Hong Jiang

In this paper, we propose a hole-filling based memory controller of a disparity modification system for multiview three-dimensional video. Three-dimensional video provides realistic perception and is one component of the next generation of video. The key technique for three-dimensional displays is accurate disparity recording and hole filling in multiview three-dimensional video. In order to solve these problems, we present a hole-filling based memory controller to repair incorrect depth values using a hole-filling recorder in multiview three-dimensional video. Also, we adopt a three-camera approach to record the multiview stereo video and modify disparities in the system.


IEEE Transactions on Magnetics | 2014

3-D Holographic Data Storage Circuit Design

Yu-Cheng Fan; Chun-Chang Lu; Di-Wei Syu; Sin-Hong Chen; Yun-Ting Shie

In this paper, we propose a 3-D holographic data storage circuit design. According to optical principle, holographic data storage and processing circuit are designed to record the holographic image and achieve 3-D holographic display. The circuit performs the rotation, mirror, and shift operation of holographic image and calibrates the stereo panoramic imaging system. In the system, multirate operating is adopted to achieve holographic image resizing. Simultaneously, holographic image calibration is performed to achieve smooth panoramic stereo image. After designing, the system provides fantasy 3-D holographic images that attract human attention.


IEEE Transactions on Magnetics | 2009

A New Method for High-Speed Dynamic TSPC Memory by Low-Temperature Poly Silicon TFT Technology

Yu-Cheng Fan; Ta-Che Lo

We propose an 8 by 8 dynamic true-single-phase-clock (TSPC) circuit based on low-temperature polycrystalline silicon (LTPS) technology to perform high speed dynamic memory cell. The proposed method allows the memory access rate to reach 25 MHz, in contrast to the traditional LTPS memory, with static circuit design, that operates at a low frequency of only about 6 MHZ. The 8 by 8 dynamic TSPC LTPS memory cell can be applied in high speed circuits. The experimental results show that the proposed 8 by 8 dynamic TSPC LTPS memory cell, operating at 25 MHz, can achieve high speed effectively. We believe it will be the most suitable technology to realize high speed memory for system on a panel (SOP) together with IC chip technology.


IEEE Transactions on Magnetics | 2009

High-Speed Memory Cell Circuit Design Based on Low-Temperature Poly Silicon TFT Technology

Yu-Cheng Fan; Yi-Cheng Liu

In this paper, low-temperature poly-silicon (LTPS) thin-film transistors (TFT) are used for LTPS memory on glass substrates. System on panel (SOP), combined with memory, controller, and driver circuits on a glass substrate, will be the most suitable applications for TFT panels in the near future. Recently, the low-temperature poly-silicon thin-film transistors prepared on glass substrates have been studied extensively. Compared to amorphous silicon TFT (a-Si TFT), the LTPS TFT has electron mobility that is several orders of magnitude higher. Therefore, it is possible to integrate the LTPS TFT with peripheral circuits on the same glass substrate for advanced flat panel display applications. We use LTPS technology to achieve a high-speed memory cell that adopts a true single phase clocking (TSPC) circuit. Finally, the experimental results show that the high-speed TSPC LTPS-TFT memory operates at 24 MHz and accomplishes the SOP design target.


IEEE Transactions on Magnetics | 2014

Luminance and Color Correction of Multiview Image Compression for 3-DTV System

Yu-Cheng Fan; Jun-Lin You; Jan-Hung Shen; Chun-Hung Wang

In this paper, we propose a luminance and color correction scheme for multiview image compression for a 3-DTV system. According to characteristics of luminance and chrominance, we propose a 3-D discrete cosine transform (3-D DCT) for 3-D image compression. Then, a cubic memory-based 3-D DCT is proposed for 3-D image compression in this paper. 3-D display technology has become an important technology lately. TFT-based multiview 3-D display has the advantage of convenient setup, mass production, and a large amount of 3-D content support, making it a popular 3-D display product. However, multiview 3-D signals need huge storage space and wide channel bandwidth, especially when view number is larger than two views. To overcome the obstacles, we propose a 3-D DCT component based on cubic memory to perform 3-D image compression in this paper. The presented architecture reduces a great quantity of memory space and provides efficient 3-D signal storage.


IEEE Transactions on Magnetics | 2009

Oblique Memory Array Design Method

Yu-Cheng Fan; Yi-Chun Chen

In this paper, we propose an efficacious memory array design method for low temperature poly-silicon technique. According to the four steps of our suggested method, we can draw a regular layout form of memory array. The regular property allows both ready calculation of the layout area and easy design of the memory controller. Since our proposed method does not leave any gaps in our layout, it is a powerful way to save area in the LTPS technique. It is also suitable for an electronic design automation (EDA) tool to implement a memory compiler with systematic and required size memory IP. Since the true single phase clock (TSPC) master-slave latch (MSL) is a fast and simple structure to implement a clocked storage element, we use TSPC-MSL as our memory cells to increase working frequency by a wide margin. Furthermore, according to our oblique memory array design method, we propose a verification formula to double-check whether our design is optimal or not at any time.


systems, man and cybernetics | 2015

Three Dimensional Gestures Interface Based on Complex Background for Intelligent Internet Systems

Yu-Cheng Fan; Chun-Hung Wang; Chun-Chang Lu

In this paper, we propose a three dimensional gestures interface based on complex background for intelligent Internet systems. Our system could be used in illumination changes, varying color and cluttered background. Avoid affecting the system accuracy from the different environment. Furthermore, the system recognized the state of users hand and fingers via information. Our system provided a human-computer interaction (HCI) by using gesture for intelligent Internet systems application.

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Chun-Hung Wang

National Taipei University of Technology

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Bing-Lian Lin

National Taipei University of Technology

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Chih-Kang Lin

National Taipei University of Technology

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Chun-Chang Lu

National Taipei University of Technology

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Hung-Kuan Liu

National Taipei University of Technology

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Shih-Ying Chou

National Taipei University of Technology

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Shu-Hsien Wu

National Taipei University of Technology

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Chih-Cheng Lu

Industrial Technology Research Institute

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Di-Wei Syu

National Taipei University of Technology

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Jan-Hung Shen

National Taipei University of Technology

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