Chun-Chang Lu

Device and reliability of high-k Al/sub 2/O/sub 3/ gate dielectric with good mobility and low D/sub it/

We report a very simple process to fabricate Al/sub 2/O/sub 3/ gate dielectric for CMOS technology with k (9.0 to 9.8) greater than Si/sub 3/N/sub 4/. Al/sub 2/O/sub 3/ is formed by direct oxidation from thermally evaporated Al. The 48 /spl Aring/ Al/sub 2/O/sub 3/ has /spl sim/7 orders lower leakage current than equivalent 21 /spl Aring/ SiO/sub 2/. A good Al/sub 2/O/sub 3/-Si interface was evidenced by the low interface density of 1/spl times/10/sup 11/ eVcm/sup -2/ and compatible electron mobility with thermal SiO/sub 2/. Good reliability is measured from the small stress induced leakage current (SILC) after 2.5 V stress for 10,000 s.

Improved Electrical Characteristics of Ge pMOSFETs With ZrO 2 /HfO 2 Stack Gate Dielectric

Electrical characteristics of Ge pMOSFETs with HfO₂, ZrO₂, ZrO₂/HfO₂, and HfZrO_x gate dielectrics are studied in this letter. A lower equivalent oxide thickness (EOT) is obtained in ZrO² device, which, however, has a higher interface trap density (D_it) due to its inferior dielectric/Ge interface. Interestingly, the Dit and sub-threshold swing of Ge pMOSFETs are clearly reduced by ZrO₂/HfO₂ stack gate dielectric. A peak hole mobility of 335 cm²/V-s is achieved in ZrO₂/HfO₂ device thanks to good dielectric/Ge interface. Furthermore, the EOT of ZrO₂/HfO₂ device is 0.62 nm, and the leakage current is 2 × 10^-3 A/cm². Therefore, a ZrO₂/HfO₂ stack gate dielectric is promising for Ge MOSFETs.

An Ultralow EOT Ge MOS Device With Tetragonal HfO 2 and High Quality Hf x Ge y O Interfacial Layer

A Ge MOS device with an ultralow equivalent oxide thickness of ~0.5 nm and acceptable leakage current of 0.5 A/cm2 is presented in this paper. The superior characteristics can be attributed to a tetragonal HfO2 with a higher k value (k ~ 31) and comparable bandgap. In addition, a Ge MOS device with tetragonal phase HfO2 (t-HfO2) also shows a lower leakage current and better thermal stability. The mechanisms for t-HfO2 formation may be explained by the little Ge diffusion from Ge substrate and oxygen deficiency, which are obtained by in situ interfacial layer (IL) formation and high-k processes. The IL with k ~ 13 can be formed by in situ H2O plasma treatment. Moreover, a Ge MOS device with the IL grown by H2O plasma shows smaller interface trap density and hysteresis effects due to a high composition of Ge+4.

Improved Electrical Characteristics of Ge MOS Devices With High Oxidation State in

Ge MOS devices with about 95% Ge4+ in HfGeOx interfacial layer are obtained by H2O plasma process together with in situ desorption before atomic layer deposition (ALD). The equivalent oxide thickness is scaled down to 0.39 nm; the leakage current is decreased as well. The improvement can be attributed to the in situ Ge suboxide desorption process in an ALD chamber at 370 °C. The interface trap density and frequency dispersion need further process development to be reduced.

{\rm HfGeO}_{\rm x}

Since the SiGe or Ge channel materials are desirable to enhance the carrier mobility degraded by ultrathin high-k gate dielectric, the pMOSFET device with novel superlattice (SL) SiGe channels is proposed in this letter. Experimental results show that the electrical characteristics of MOSFET can be obviously improved by an SL virtual substrate. The peak hole mobility of the pMOSFET device with SL is enhanced by about 100% as compared to that with the Si one. The on-off ratio of the Id-Vg curve is beyond eight orders, and the electrical thickness in inversion (Tinv) value of the gate dielectric can be ~1.4 nm. The source/drain activation temperature of 650°C is particularly suitable to high-k dielectric process.

Interfacial Layer Formed by In Situ Desorption

A novel charge-pumping (CP) technique is demonstrated to extract border-trap distribution for high- kappa gated MOSFETs. The varying-frequency CP method is shown to be more effective than the varying-amplitude one for probing border traps and extending the tunneling depth. A linear relationship of the Qcp versus ln(T rTf)1/2 plot can only be maintained at the CP frequency of 1 MHz, while not below 1 MHz, due to the influence of border traps near HfOxNy/Si interface. The proposed technique, which takes into consideration the effect of carrier tunneling in slow oxide traps, is used successfully to obtain the spatial and energy dependence of bulk trap density in high-kappa bulk

Enhanced Hole Mobility and Low

To better understand the channel-hot-carrier (CHC)-induced reliability problems, a modified charge-pumping (CP) technique is proposed to characterize the distribution profiles of trap generation in MOSFETs with high- k gate-stack. The effects of gate leakage current on CP measurements were minimized to ensure the correct CP data. While applying dynamic drain bias, the gate-induced drain leakage current is also considered to get correct CP data. Through the CP with dynamic drain bias and various gate pulse frequencies, the profiling of CHC stress-induced interface- and border-traps can be achieved. The CHC stress-induced interface trap generation appears along whole the channel but that-induced border trap generation is mainly located above the pinchoff region near the drain and decreases dramatically toward the center of the channel. Thus, the CHC stress causes quite localized border trap generation at the gate-edge region inside the high- k dielectric. The reliability data measured by CP with different gate voltage swings confirm that CHC stress causes interface trap generation through whole the channel and significant border trap generation at gate-edge region.

Tinv

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO2-dominated high-k gate dielectrics is like mobile defect; while that with SiO2-dominated ones is similar to the near-interface/border trap.

for pMOSFET by a Novel Epitaxial Si/Ge Superlattice Channel

A stress-and-sense charge pumping (SSCP) technique is proposed in this paper to measure the stress-induced interface trap (ΔN_it) in real-time evolution without stress interruption. Results show that the ΔN_it measured by this SSCP technique is much higher than that measured by the conventional method. This difference is resulted from the recovery induced by stress interruption during the sensing measurements. The ΔN_it measured by SSCP method after interruption is approximately equal to that by the conventional one. The amount of recoverable ΔN_it is almost constant and independent of permanent damage. The stress-induced threshold voltage shift (ΔV_th) and ΔN_it under various stress frequencies and duty cycles are also measured. The ΔV_th seems to depend only on the total stress time of stress pulse. The ΔN_it measured by SSCP with different frequencies and duty cycles is similar. The ΔN_it also depends on the total stress time of stress pulse, but not the off time during the nonstress half cycle. In addition, it is found that the recovery induced by nonstress half cycle of ac stress is almost negligible as compared with that induced by stress interruption. Moreover, a two-stage phenomenon is observed on ΔN_it evolution. Results in this paper indicate that the stressing indeed induces trap generation in the first stage.

Detection of Border Trap Density and Energy Distribution Along the Gate Dielectric Bulk of High-

The TaN/HfON/GeO₂/n-Ge pMOSFETs were fabricated with different formation processes of GeO₂ interfacial layer. Ultra low EOT of around 0.5 nm is achieved using GeO₂ grown by H₂O plasma together with in-situ grown HfON gate dielectric, and simultaneously the peak hole mobility of Ge pMOSFET is 312 cm²/V*s.