Yu Chien Chiu
National Chiao Tung University
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Publication
Featured researches published by Yu Chien Chiu.
IEEE\/OSA Journal of Display Technology | 2014
Hsiao Hsuan Hsu; Chun-Yen Chang; Chun Hu Cheng; Po Chun Chen; Yu Chien Chiu; Ping Chiou; Chin Pao Cheng
This paper reports an InGaZnO thin-film transistor (TFT) that involves using fully room-temperature gate dielectrics on a flexible substrate. The wide bandgap dielectrics of HfO<sub>2</sub> and Y<sub>2</sub>O<sub>3</sub> exhibited favorable adhesion properties on a flexible substrate compared with conventional low-κ SiO<sub>2</sub> film. Based on the experimental results, the room-temperature IGZO/HfO2 TFTs demonstrated effective device integrity, and achieve a low drive voltage of V, a low threshold voltage of 0.46 ±006 V, a low sub-threshold swing of 110 ±6 mV/decade and an extremely high mobility of 60.2 ±32 cm <sup>2</sup>/V·s. The excellent performance of this TFT indicated that it demonstrates considerable potential for active-matrix liquid crystal display applications requiring low power consumption and a high driving current.
symposium on vlsi technology | 2015
Yu Chien Chiu; Chun Hu Cheng; Chun-Yen Chang; M. H. Lee; Hsiao Hsuan Hsu; Shiang Shiou Yen
In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10<sup>-15</sup> A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔV<sub>T</sub> window of 2.8V, fast 20-ns speed, 10<sup>3</sup>s retention at 85°C, and long extrapolated 10<sup>16</sup> endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.
IEEE Transactions on Nanotechnology | 2014
Hsiao Hsuan Hsu; Chun-Yen Chang; Chun Hu Cheng; Shan Haw Chiou; Chiung Hui Huang; Yu Chien Chiu
This study involved developing a low-power and high-mobility metal-oxide thin-film transistor that incorporated a bilayer IGZO/IGZO:Ti semiconductor material. Compared with control metal-oxide TFTs, the bilayer IGZO TFT through thickness modulation of IGZO:Ti can reach the smallest subthreshold swing (85 mV/decade) and the highest field effect mobility (49 cm2/Vs) at a drive voltage of <;3 V. This performance level improvement can be attributed to the gettering effect caused by the IGZO:Ti capping layer and its dual advantages, which enhance device mobility and improve gate swing.
IEEE\/OSA Journal of Display Technology | 2016
P. C. Chen; Yung-Hsien Wu; Z. W. Zheng; Yu Chien Chiu; Chun Hu Cheng; Shiang Shiou Yen; Hsiao Hsuan Hsu; Chun-Yen Chang
In this paper, we investigated the bipolar conduction mechanism in thin-film transistors (TFTs) with oxygen plasma treatment on tin-oxide channel. The optimized p-type thin-oxide TFTs showed an on/off ratio of > 104, a threshold voltage of -1.05 V, and a field-effect mobility of 2.14 cm2·V-1·s-1. By increasing the exposure time of oxygen plasma, excess oxygen was incorporated to thin-oxide channel and converted thin monoxide to oxygen-rich n-type thin dioxide, which in turn led to n-type operation. It indicated that oxygen plasma was the critical factor to determine oxygen concentration, oxygen vacancies, metal ions and channel polarity. This proposed oxygen-content tuning through plasma treatment approach shows great promise in simplification of TFT process that can achieve n-type and p-type TFTs under the same device process.
IEEE\/OSA Journal of Display Technology | 2016
Shiang Shiou Yen; Yu Chien Chiu; Chun Hu Cheng; P. C. Chen; Yu Chen Yeh; Chien Hung Tung; Hsiao Hsuan Hsu; Chun-Yen Chang
This paper reported the IGZO and IZO thin-film transistor (TFT) with titanium-oxide semiconductor as channel capping layer. After the TiOx Gettering process, the oxygen vacancies in IGZO channel were successfully modified to maximize the carrier concentration and device mobility. The superior transfer characteristics included a low sub-threshold swing of 79 mV/decade, a very high mobility of 68 cm2/V·s, and good on/off-current ratio of 5.61×106. However, the IZO channel with nano-crystallized grains and without Ga atom doping showed unfavorable transistor characteristics. In addition to apparently degraded transfer properties, the spontaneously oxidized TiOx capping layer also lead to an increase of channel parasitic resistance that limits the output driving current. Therefore, we believe that the existence of Ga-O bonds among IGZO channel would be helpful to stabilize oxygen diffusion behavior and electric structure during Gettering process.
international reliability physics symposium | 2015
Yu Chien Chiu; Chun-Yen Chang; Hsiao Hsuan Hsu; Chun Hu Cheng; M. H. Lee
We demonstrate a novel hybrid nonvolatile memory integrated with a charge trapping mechanism and a ferroelectric polarization effect. The hybrid memory features a large threshold voltage window of 2V, fast 20-ns program/erase time, tight switching margin, and long 1012-cycling endurance at 85oC. Such excellent endurance reliability at 85°C can be ascribed to the introduction of charge-trapping node into the design of memory structure that not only weakens temperature-dependent polarization relaxation, but also improves high-temperature endurance reliability.
IEEE Electron Device Letters | 2017
P. C. Chen; Yu Chien Chiu; Guan Lin Liou; Z. W. Zheng; Chun Hu Cheng; Yung-Hsien Wu
This letter reports on a tin oxide (SnO) thin-film transistor (TFT) with p-type conduction that uses aluminum (Al) doping in the SnO active channel layer. Performance enhancements were further achieved by applying fluorine plasma treatment on the p-type Al-doped SnO channel layer. The effects of the fluorine plasma treatment were also investigated. By tuning the power of the fluorine plasma treatment on the p-type Al-doped SnO channel layer, the optimal TFT device showed a very high on/off current ratio of
symposium on vlsi technology | 2016
Yu Chien Chiu; Chun Hu Cheng; Chun-Yen Chang; Ying Tsan Tang; Min Cheng Chen
2.58\times 10^{\mathrm {6}}
IEEE\/OSA Journal of Display Technology | 2015
Hsiao Hsuan Hsu; Chun Hu Cheng; Ping Chiou; Yu Chien Chiu; Shiang Shiou Yen; Chien Hung Tung; Chun-Yen Chang
and a low threshold swing of 174 mV/decade, which could be attributed to the passivation effect of the plasma fluorination on the dominant donor-like traps at the SnO/HfO2 interface, as reflected by the suppression of the hysteresis phenomenon, the low density of interface traps, and the small subthreshold swing. The results indicate that the p-type Al-doped SnO TFT device with fluorine plasma treatment has considerable potential for application in future high-performance displays.
symposium on vlsi technology | 2017
Chih-Chiang Wu; Shih-Chien Liu; Chung Kai Huang; Yu Chien Chiu; P. C. Han; Po-Chun Chang; Franky Lumbantoruan; Chia-Ching Lin; Yu-Hsuan Lin; C. Y. Chang; Chenming Hu; Hiroshi Iwai; Edward Yi Chang
In this work, we report a ferroelectric versatile memory (FE-VM) with strained-gate engineering. The memory window of high strain case was improved by ~47% at the same ferroelectric thickness, which agrees with the increase of orthorhombic crystallinity. Based on a reliable first principle calculation (FPC), we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. On the other hand, the orthorhombic FE-AFE phase transition plays a key role in realizing negative capacitance (NC) effect at high gate electric field. This 1T strained-gate FE-VM with ferroelectric NC achieves a sub-60-mVdec subthreshold swing (SS) over ~4 decade of ID to provide a 1~10 fA/μm Ioff and >108 Ion/Ioff ratio, which allows for a fast 20-ns P/E switching during 1012 cycling endurance.