Chun-Yen Chang

Specific contact resistance of metal-semiconductor barriers

Abstract The specific contact resistance at zero bias, R c , serves as a measure of the ohmic or rectifying behavior of a metal-semiconductor barrier under operating conditions. It is thus an important design parameter for semiconductor devices. The values of R c have been calculated for Metal-Si and metal-GaAs barriers on p -type and n -type samples. The theoretical calculation is based on the generalized transport study of metal-semiconductor systems. The results, which are presented graphically, show the dependence of R c on temperature over the range 50°K–500°K, the barrier height from 0.2 to 1.0 eV, and the ionized impurity concentration from 10 14 to 10 21 cm −3 . Generally R c decreases exponentially with increasing temperature and with decreasing barrier height. For samples with lower dopings where the thermionic emission dominates, R c is essentially independent of doping; for higher dopings where the tunneling dominates, R c decreases rapidly with increasing doping. The experimental results of R c for various metals on silicon samples are in good agreement with the predictions.

Carrier transport across metal-semiconductor barriers

Abstract Carrier transport across metal-semiconductor barriers has been studied theoretically and experimentally to give a generalized and quantitative presentation. The thermionic and tunneling processes have been analyzed in terms of accurate quantum transmission coefficients. The effects of image-force lowering, temperature, and two-dimensional statistical variation of impurity concentration have also been incorporated in the theory. Theoretical results give a description of the current transport, due to combined effect of tunneling and thermionic emission over a temperature range from essentially absolute zero to the highest practical temperatures, and over doping densities from 1014 cm−3 to complete degeneracy. An interesting result of the analysis is the existence of a minimum in the saturation current density Js near 1016 cm−3; the current density rises slightly at lower dopings because of enhanced transmission coefficient for thermionic emission and increases drastically at higher dopings because of tunneling. For example for PtSiSi system at 300°K with a barrier height of 0.85 eV, Js is 80 nA/cm2 at 1014 cm−3, reaches a minimum of 60 nA/cm2 at 1016 cm−3, then rapidly increases to 103 A/cm2 at 1020 cm−3. In the high doping range the average saturation current density is considerably increased by the effect of two-dimensional impurity variation. The room-temperature transition doping for breakdown in metal-silicon systems occurs at 8×1017 cm−3; for lower dopings the breakdown is due to avalanche multiplication, and for higher dopings it is due to tunneling of carriers from the metal Fermi level to semiconductor bands. The metal-silicon diodes were fabricated by planar technology with guard-ring structures to eliminate edge effects. Extensive experimental studies, including current-voltage, capacitance-voltage, and photoelectric measurements covering the doping range from 1014 to 1020 cm−3 and the temperature range from 77°K to 373°K, gave good agreement with theoretical predictions.

Reliability characteristics of NiSi nanocrystals embedded in oxide and nitride layers for nonvolatile memory application

The authors provided the reliability characteristics of nonvolatile nickel-silicide nanocrystal memories embedded in oxide and nitride layers for next-generation nonvolatile memory application. The charge trapping layer was deposited by sputtering a commixed target in the argon and oxygen/nitrogen ambiances, and then using a low temperature rapid thermal annealing to form nanocrystals. Transmission electron microscope clearly shows the sharpness and the density of nanocrystals. These proposed memory structures were compared for the charge storage ability, retention, and endurance. In addition, we used a simple simulation of electric field for nonvolatile nanocrystals memory to explain the advantages by using the high-k dielectric.

High-performance nonvolatile HfO/sub 2/ nanocrystal memory

In this letter, we demonstrate high-performance nonvolatile HfO/sub 2/ nanocrystal memory utilizing spinodal phase separation of Hf-silicate thin film by 900/spl deg/C rapid thermal annealing. With this technique, a remarkably high nanocrystal density of as high as 0.9 /spl sim/ 1.9 /spl times/ 10/sup 12/ cm/sup -2/ with an average size <10 nm can be easily achieved. Because HfO/sub 2/ nanocrystals are well embedded inside an SiO/sub 2/-rich matrix and due to their sufficiently deep energy level, we, for the first time, have demonstrated superior characteristics of the nanocrystal memories in terms of a considerably large memory window, high-speed program/erase (P/E) (1 /spl mu/s/0.1 ms), long retention time greater than 10/sup 8/ s for 10% charge loss, and excellent endurance after 10/sup 6/ P/E cycles.

A Flexible IGZO Thin-Film Transistor With Stacked

This letter demonstrates the feasibility of full room temperature InGaZnO thin-film transistor (TFT) using trilayer gate dielectric on flexible substrate. Through integrating high-κ SiO₂/TiO₂/SiO₂ (STS) gate-stack as well as InGaZnO channel thickness modulation, the resulting flexible indium-gallium-zinc oxide (IGZO)/STS TFTs show low threshold voltage of 0.5 V, small subthreshold swing of 0.129 V/decade, high field effect mobility of 76 cm²/Vs , and good I_ON/I_OFF ratio of 6.7×10⁵, which have the potential for the application of high-resolution flexible display.

{\rm TiO}_{2}

In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (Vth) , and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.

-Based Dielectrics Fabricated at Room Temperature

The formation of stacked Ni silicide nanocrystals by using a comixed target is proposed in this letter. High resolution transmission electron microscope analysis clearly shows the stacked nanocrystals embedded in the silicon oxide. The memory window enough to define “1” and “0” states is obviously observed at low voltage programming conditions, and good data retention characteristics are exhibited for the nonvolatile memory application. A physical model is also proposed further to explain the saturation phenomenon of threshold voltage at different programming voltages with operation duration.

A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory

P-channel MOS transistors with raised Si/sub 1-x/Ge/sub x/ and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si/sub 1-x/Ge/sub x/ and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si/sub 1-x/Ge/sub x/ S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R/sub SD/), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R/sub SD/ of devices with Si/sub 1-x/Ge/sub x/ raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g/sub m/) at an effective channel length of 0.16 /spl mu/m. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si/sub 1-x/Ge/sub x/ S/D structure very attractive for future sub-0.1 /spl mu/m p-channel MOS transistors.

Formation of stacked Ni silicide nanocrystals for nonvolatile memory application

The efficiency droop in InGaN-based UV light emitting device (LED) with AlGaN and InAlGaN barrier is investigated. Electroluminescence results indicate that the light performance of quaternary LEDs can be enhanced by 25% and 55% at 350 mA and 1000 mA, respectively. Furthermore, simulations show that quaternary LEDs exhibit 62% higher radiative recombination rate and low efficiency degradation of 13% at a high injection current. We attribute this improvement to increasing of carrier concentration and uniform redistribution of carriers.

Reduction of source/drain series resistance and its impact on device performance for PMOS transistors with raised Si/sub 1-x/Ge x source/drain

The organic silsesquioxane, methylsilsesquioxane (MSQ), has a low dielectric constant because of its lower film density compared to thermal oxide. However, the quality of MSQ film is degraded by the damage of oxygen plasma and hygroscopic behavior during photoresist stripping. In this work, we studied the N 2 O plasma treatment for improving the quality of MSQ. The leakage current of MSQ decreases as the N 2 O plasma treatment time is increased. The dielectric constant of N 2 O plasma-treated sample remains constant (∼2.7). In addition, the thermal stability of MSQ film can be enhanced. The role of N 2 O plasma is to convert the surface layer of organic MSQ into inorganic type by decomposition of the alkyl group and thus form a passivation layer. The inert passivation layer enhances the resistance to moisture uptake and O 2 plasma attack. Therefore, N 2 O plasma-treatment greatly improves the quality of low k MSQ film and removes the issue of photoresist stripping in the integrated process.