Yu-Hsin Chang

A 60 GHz CMOS VCO Using a Fourth-Order Resonator

In this letter, a 60 GHz voltage-controlled oscillator (VCO) implemented in the 90 nm CMOS process is presented. By using a fourth-order LC resonator, the proposed VCO oscillates at its second pole frequency to achieve high speed operation with fully differential output phases and a wide tuning range with a larger size of varactors. The measured oscillation frequencies of the proposed VCO are from 58.76 to 63.94 GHz corresponding to an 8.44% tuning range. The measured phase noise is -91.53 dBc/Hz at 1 MHz frequency offset for the highest output frequency. The core circuit consumes 7.2 mW power from a 1.2 V dc supply.

A V-Band Push-Push VCO With Wide Tuning Range Using

A V-band push-push voltage-controlled oscillator (VCO) with wide tuning range implemented in the 0.18 μm CMOS process technology is presented in this letter. The output signal with frequency twice that of the VCO core is extracted from the center tap of inductors rather than the one-quarter wavelength transmission line. The measured oscillating frequency of the VCO is from 67.18 to 74.84 GHz corresponding to a 10.79% tuning range. At the 74.84 GHz output frequency, the measured phase noises at 1 MHz and 10 MHz frequency offsets are -74.83 dBc/Hz and -102.53 dBc/Hz, respectively. The core circuit draws a 13.5 mA current from a 1.8 V power supply.

0.18~\mu{\rm m}

A 4.03GHz–4.97GHz quadrature voltage-controlled oscillator (QVCO) with back-gate coupling and VCO gain (Kvco) linearization techniques implemented in 0.35μm SiGe BiCMOS process technology is presented. The back-gate coupling is adopted to improve the phase noise and to reduce the power consumption, and a voltage-level-shift circuit is used to linearize the VCO gain. The core circuit draws a 5.65mA current from 3.0V power supply. The measured phase noise at 1MHz frequency offset is −102.76dBc/Hz. And the measured Kvco is from 456MHz/V to 744MHz/V with a Kvco ratio of 1.63.

CMOS Process

A divide-by-3 injection-locked frequency divider (ILFD) implemented in the 0.18 μm CMOS process is proposed for K band applications. The proposed ILFD adopts the stacked cross-coupled transistor pair topology to enhance the required frequency component and to reduce dc power consumption. Without the help of varactors, the measured locking range of the proposed ILFD is from 20.4 to 23.8 GHz under 0-dBm input power level. The core circuit dissipates 3.9 mW power from a 1.5-V dc supply.