Ching-Yuan Yang

A wide-range delay-locked loop with a fixed latency of one clock cycle

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N/spl times/T/sub Dmax/) to 1/(3T/sub Dmin/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 /spl mu/m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz.

Fast-switching frequency synthesizer with a discriminator-aided phase detector

A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-/spl mu/m CMOS process, and the output phase noise is -99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its power consumption is 120 mW.

Clock-deskew buffer using a SAR-controlled delay-locked loop

A successive approximation register-controlled delay-locked loop (SARDLL) has been fabricated in a 0.25-/spl mu/m standard n-well DPTM CMOS process to realize a fast-lock clock-deskew buffer for long distance clock distribution. This DLL adopts a binary search method to shorten lock time while maintaining tight synchronization between input and output clocks. The measured lock time of the proposed SARDLL is within 30 clock cycles at 100-MWz clock input. The power dissipation is 3.3 mW (not including off-chip drivers) at a 1.1-V supply voltage while the measured rms and peak-to-peak jitter are 11.3 ps and 95 /spl mu/s, respectively.

New dynamic flip-flops for high-speed dual-modulus prescaler

A fast pipeline technique using single-phase, edge-triggered, ratioed, high-speed logic flip-flops and D flip-flops is introduced and analyzed. The circuits achieve high speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. Also it is suitable for realizing high-speed synchronous counters. A divide-by-128/129 and 64/65 dual-modulus prescaler using the proposed flip-flops is measured in 0.8 /spl mu/m CMOS technology with the operating clock frequency reaching as high as 1.8 GHz.

A one-wire approach for skew-compensating clock distribution based on bidirectional techniques

A clock-deskew buffer using the delay-locked loop and the bidirectional technique has been developed. It needs only one wire to synchronize the clocks for a chip-to-chip system. It has been fabricated by a 0.35-/spl mu/m n-well CMOS process. Experimental results demonstrate that it can achieve the peak-to-peak jitter smaller than 100 ps through a two-meter coaxial cable while operating at the frequency of 120 MHz. The total power dissipation of the skew buffer is 218 mW for a 3 V supply. The core chip area is 980/spl times/1700 /spl mu/m/sup 2/.

A

A triangular-modulated spread-spectrum clock generator using a Delta-Sigma-modulated fractional-N phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased Delta-Sigma operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of plusmn0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies 950 times 850 mum2 in 0.18-mum CMOS process and consumes 36 mW.

\Delta{-}\Sigma

A 1-Gb/s 0.18- mum CMOS serial-link transceiver using multilevel pulse-width and pulse-amplitude modulation (PWAM) signaling and a pre-emphasis technique is presented. Based on the PWAM technique, the transmit signaling is implemented to effectively push high data rates through bandwidth- limited channels. The clock is implicitly embedded in the 4-bit data stream, and the associated overhead needed in the clock-and-data recovery circuitry can be mitigated. In addition, the pin count can be reduced by transferring the data channels and the clock channel over a single transmitted channel. The recovered clock has an rms jitter of 5.9 ps at 250 MHz, and the retimed data have an rms jitter of 13.7 ps at 250 Mb/s. The occupied die area is 1.65 X 1.40 mm2. The transmitter and receiver power consumption is 86 and 45 mW, respectively.

PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology

A direct digital frequency synthesizer (DDFS) using an analog-sine-mapping technique is presented in a 0.35-μm SiGe BiCMOS process. We intend to apply the translinear principle to develop a triangle-to-sine converter (TSC) that can achieve outputs with low harmonic content. The TSC is introduced for the DDFS to translate phase data to sine wave. Using this analog-interpolating technique, the DDFS, with 9 bits of phase resolution and 8 bits of amplitude resolution, can achieve operation at 5-GHz clock frequency and can further reduce power consumption and die area. The spurious-free dynamic range (SFDR) of the DDFS is better than 48 dBc at low synthesized frequencies, decreasing to 45.7 dBc worst case at the Nyquist synthesized frequency for output frequency band (0-2.5 GHz). The DDFS consumes 460 mW at a 3.3-V supply and achieves a high power efficiency figure of merit (FOM) of 10.87 GHz/W. The chip occupies 1.5 × 1.4 mm2.

A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers

A 900-MHz 1-V frequency synthesizer has been fabricated in a standard 0.35-/spl mu/m CMOS technology. The frequency synthesizer consists of a divide-by-128/129 and 64/65 dual-modulus prescaler, phase-frequency detector, charge pump, and voltage-doubler circuit with an external voltage-controlled oscillator (VCO) and passive loop filter. The on-chip voltage-doubler circuit converts the 1-V supply voltage to the higher voltage which supplies the prescaler internally. In this way, the 900-MHz 1-V frequency synthesizer with an external VCO can be achieved. The measured phase noise is -112.7 dBc/Hz at a 100-kHz offset from the carrier, and the synthesizer dissipates 3.56 mW (not including VCOs) from a single 1-V supply when the switching frequency of the on-chip voltage doubler is 200 kHz and the power efficiency of the voltage doubler is 77.8%. The total chip area occupies 0.73 mm/sup 2/.

A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35-

Without an extra on-chip accumulation-mode MOS varactor, a voltage-controlled oscillator (VCO) using a negative-transconductance back-gate tuned technique is demonstrated in a standard 0.18 μm CMOS process to achieve low-voltage, wide-range and high-frequency designs. Employing the varied p-n junction capacitance and the varied transconductance in the intrinsic-tuned regime, the VCO provides the tuning range of 9.95 to 11.05 GHz at a 0.6 V supply and dissipates below 4.35 mW. At 11 GHz carrier frequency, the measured phase noise is -110.4 dBc/Hz at a 1 MHz offset.