Yu Nishitani

Three-terminal ferroelectric synapse device with concurrent learning function for artificial neural networks

Spike-timing-dependent synaptic plasticity (STDP) is demonstrated in a synapse device based on a ferroelectric-gate field-effect transistor (FeFET). STDP is a key of the learning functions observed in human brains, where the synaptic weight changes only depending on the spike timing of the pre- and post-neurons. The FeFET is composed of the stacked oxide materials with ZnO/Pr(Zr,Ti)O3 (PZT)/SrRuO3. In the FeFET, the channel conductance can be altered depending on the density of electrons induced by the polarization of PZT film, which can be controlled by applying the gate voltage in a non-volatile manner. Applying a pulse gate voltage enables the multi-valued modulation of the conductance, which is expected to be caused by a change in PZT polarization. This variation depends on the height and the duration of the pulse gate voltage. Utilizing these characteristics, symmetric and asymmetric STDP learning functions are successfully implemented in the FeFET-based synapse device by applying the non-linear puls...

Ferroelectric Artificial Synapses for Recognition of a Multishaded Image

We demonstrate, for the first time, the on-chip pattern recognition of a multishaded grayscale image in a neural network circuit with multiple neurons. This pattern recognition is based on a spiking neural network model that uses multiple three-terminal ferroelectric memristors (3T-FeMEMs) as synapses. The synapse chip of the neural network is formed by stacking CMOS circuits and 3T-FeMEMs. The conductance of the 3T-FeMEM is gradually changed in the linear range by varying the amplitude of the applied voltage pulse. Using the analog and nonvolatile conductance change of the 3T-FeMEM as synaptic weight, the matrix patterns are learned after the spike timing-dependent plasticity learning rule. Even when an incomplete multishaded pattern is input to the neural network circuit, it automatically completes and recalls a previously learned pattern.

A 60 nm channel length ferroelectric-gate field-effect transistor capable of fast switching and multilevel programming

We demonstrate a 60 nm channel length ferroelectric-gate field-effect transistor (FeFET) with thin-film transistor structure and good electrical properties. The FeFET contains three oxide thin-films: SrRuO3 (bottom gate electrode), Pb(Zr,Ti)O3 (ferroelectric), ZnO (semiconductor). The FeFET drain current-bottom gate voltage (IDS−VGS) characteristics show a high ON/OFF ratio of 105. The drain current ON/OFF ratio was about three orders of magnitude for write pulse widths as narrow as 10 ns. Although the channel length is set at 60 nm, the conductance can be changed continuously by varying the write pulse width. Good retention properties for three-level data were demonstrated.

Correlated motion dynamics of electron channels and domain walls in a ferroelectric-gate thin-film transistor consisting of a ZnO/Pb(Zr,Ti)O3 stacked structure

We studied the switching dynamics of a ferroelectric-gate thin-film transistor (FeTFT) consisting entirely of oxide-based thin films: SrRuO3 (SRO: bottom-gate electrode), Pb(Zr,Ti)O3 (PZT: ferroelectric), and ZnO (semiconductor). We switched the FeTFT channel conductance by applying short pulses to the gate electrode. We found that the switching of a FeTFT was caused by the domain wall motion in a ferroelectric film. The polarization reversal starts from the region located under the source and drain electrodes and travels along the channel length direction. In addition, the domain wall velocity increases as the domain wall gets closer to the source and drain electrodes in a ferroelectric film. Therefore, a FeTFT has the scaling merit of fast operation speed.

Dynamic Observation of Brain-Like Learning in a Ferroelectric Synapse Device

A brain-like learning function was implemented in an electronic synapse device using a ferroelectric-gate field effect transistor (FeFET). The FeFET was a bottom-gate type FET with a ZnO channel and a ferroelectric Pb(Zr,Ti)O3 (PZT) gate insulator. The synaptic weight, which is represented by the channel conductance of the FeFET, is updated by applying a gate voltage through a change in the ferroelectric polarization in the PZT. A learning function based on the symmetric spike-timing dependent synaptic plasticity was implemented in the synapse device using the multilevel weight update by applying a pulse gate voltage. The dynamic weighting and learning behavior in the synapse device was observed as a change in the membrane potential in a spiking neuron circuit.

A neural network circuit using persistent interfacial conducting heterostructures

The FeFET, based on epitaxial perovskite heterostructures, is termed an OxiM. It showed persistent interfacial conduction even when the ferroelectric polarization curve was swinging on a minor loop and also showed good controllability of drain current using pulse voltages. A neuron circuit composed of OxiMs and an op-amp adder circuit showed that the gain of the neuron circuit could also be modulated smoothly by means of pulse voltages. Using a numerical model of the neuron circuit, we simulated the learning process for “exclusive OR” and achieved a good convergence characteristic.

Supervised Learning Using Spike-Timing-Dependent Plasticity of Memristive Synapses

We propose a supervised learning model that enables error backpropagation for spiking neural network hardware. The method is modeled by modifying an existing model to suit the hardware implementation. An example of a network circuit for the model is also presented. In this circuit, a three-terminal ferroelectric memristor (3T-FeMEM), which is a field-effect transistor with a gate insulator composed of ferroelectric materials, is used as an electric synapse device to store the analog synaptic weight. Our model can be implemented by reflecting the network error to the write voltage of the 3T-FeMEMs and introducing a spike-timing-dependent learning function to the device. An XOR problem was successfully demonstrated as a benchmark learning by numerical simulations using the circuit properties to estimate the learning performance. In principle, the learning time per step of this supervised learning model and the circuit is independent of the number of neurons in each layer, promising a high-speed and low-power calculation in large-scale neural networks.

Back-Propagation Operation for Analog Neural Network Hardware with Synapse Components Having Hysteresis Characteristics

To realize an analog artificial neural network hardware, the circuit element for synapse function is important because the number of synapse elements is much larger than that of neuron elements. One of the candidates for this synapse element is a ferroelectric memristor. This device functions as a voltage controllable variable resistor, which can be applied to a synapse weight. However, its conductance shows hysteresis characteristics and dispersion to the input voltage. Therefore, the conductance values vary according to the history of the height and the width of the applied pulse voltage. Due to the difficulty of controlling the accurate conductance, it is not easy to apply the back-propagation learning algorithm to the neural network hardware having memristor synapses. To solve this problem, we proposed and simulated a learning operation procedure as follows. Employing a weight perturbation technique, we derived the error change. When the error reduced, the next pulse voltage was updated according to the back-propagation learning algorithm. If the error increased the amplitude of the next voltage pulse was set in such way as to cause similar memristor conductance but in the opposite voltage scanning direction. By this operation, we could eliminate the hysteresis and confirmed that the simulation of the learning operation converged. We also adopted conductance dispersion numerically in the simulation. We examined the probability that the error decreased to a designated value within a predetermined loop number. The ferroelectric has the characteristics that the magnitude of polarization does not become smaller when voltages having the same polarity are applied. These characteristics greatly improved the probability even if the learning rate was small, if the magnitude of the dispersion is adequate. Because the dispersion of analog circuit elements is inevitable, this learning operation procedure is useful for analog neural network hardware.

Artificial synapses using ferroelectric memristors embedded with CMOS Circuit for image recognition

Memristors have attracted attention as devices for brain-inspired computing hardware, such as artificial neural networks [1]. Typical neural networks comprise multiple neurons interconnected via synapses. A synapse modulates the signal transmission strength or “weight” between two neurons. Weight controllability is essential to neural network adaptability. Therefore, it is necessary to establish an artificial synapse that can modulate its own electric conductance, which represents the weights. Some researchers have used two-terminal memristors as synapses [2,3]. However, when using conventional memristors, pulses with complex shapes corresponding to what is learned must be prepared and applied to both terminals simultaneously because of their two-terminal structures [4]. Previously, we showed that a programmable synapse function could be implemented on a three-terminal ferroelectric memristor (3T-FeMEM) fabricated on a single crystal oxide substrate, which enabled simple learning schemes [5]. In this work, synapse chips were fabricated by integrating 3T-FeMEMs on CMOS circuits. We then demonstrated on-chip associative memory function using a neural network circuit with these chips.

Biologically-inspired learning device using three-terminal ferroelectric memristor

A simple synaptic device with a spike-timing-dependent synaptic plasticity (STDP) learning function is a key device that can realize a brain-like processor. STDP is a learning mechanism of synapses in mammalian brains [1]. A memristor [2, 3] is a promising candidate for synaptic devices. However, since the conventional memristor is a two-terminal electric element and the signal magnitude at learning exceeds the processing, it is difficult to realize STDP learning by simultaneously processing the signal. We proposed a unique three-terminal memristor using a ferroelectric thin film [4]. Its three-terminal device structure enables the STDP function without disturbing the signal processing between neurons (Fig. 1). This all oxide memristor (OxiM) has a ferroelectric gate field-effect transistor structure (Fig. 2). Since the polarization of Pb(Zr,Ti)O3 film is changed by applying gate voltage (VG), the channel conductance at the ZnO / Pr(Zr,Ti)O3 interface can be modulated (Fig. 3). Memorized conductance can be maintained without fluctuation [4]. In addition, ferroelectric polarization can be modulated by changing the height and the width of the applied voltage pulse to the gate electrode. Fig. 4 shows the conduction change after applying pulse voltages.