Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Michihito Ueda is active.

Publication


Featured researches published by Michihito Ueda.


Journal of Applied Physics | 2012

Three-terminal ferroelectric synapse device with concurrent learning function for artificial neural networks

Yu Nishitani; Yukihiro Kaneko; Michihito Ueda; Takashi Morie; Eiji Fujii

Spike-timing-dependent synaptic plasticity (STDP) is demonstrated in a synapse device based on a ferroelectric-gate field-effect transistor (FeFET). STDP is a key of the learning functions observed in human brains, where the synaptic weight changes only depending on the spike timing of the pre- and post-neurons. The FeFET is composed of the stacked oxide materials with ZnO/Pr(Zr,Ti)O3 (PZT)/SrRuO3. In the FeFET, the channel conductance can be altered depending on the density of electrons induced by the polarization of PZT film, which can be controlled by applying the gate voltage in a non-volatile manner. Applying a pulse gate voltage enables the multi-valued modulation of the conductance, which is expected to be caused by a change in PZT polarization. This variation depends on the height and the duration of the pulse gate voltage. Utilizing these characteristics, symmetric and asymmetric STDP learning functions are successfully implemented in the FeFET-based synapse device by applying the non-linear puls...


IEEE Transactions on Electron Devices | 2014

Ferroelectric Artificial Synapses for Recognition of a Multishaded Image

Yukihiro Kaneko; Yu Nishitani; Michihito Ueda

We demonstrate, for the first time, the on-chip pattern recognition of a multishaded grayscale image in a neural network circuit with multiple neurons. This pattern recognition is based on a spiking neural network model that uses multiple three-terminal ferroelectric memristors (3T-FeMEMs) as synapses. The synapse chip of the neural network is formed by stacking CMOS circuits and 3T-FeMEMs. The conductance of the 3T-FeMEM is gradually changed in the linear range by varying the amplitude of the applied voltage pulse. Using the analog and nonvolatile conductance change of the 3T-FeMEM as synaptic weight, the matrix patterns are learned after the spike timing-dependent plasticity learning rule. Even when an incomplete multishaded pattern is input to the neural network circuit, it automatically completes and recalls a previously learned pattern.


BioSystems | 2007

Input-output relationship in galvanotactic response of Dictyostelium cells.

Masayuki Sato; Michihito Ueda; Hiroaki Takagi; Tomonobu M. Watanabe; Toshio Yanagida; Masahiro Ueda

Under a direct current electric field, Dictyostelium cells exhibit migration towards the cathode. To determine the input-output relationship of the cells galvanotactic response, we developed an experimental instrument in which electric signals applied to the cells are highly reproducible and the motile response are analyzed quantitatively. With no electric field, the cells moved randomly in all directions. Upon applying an electric field, cell migration speeds became about 1.3 times faster than those in the absence of an electric field. Such kinetic effects of electric fields on the migration were observed for cells stimulated between 0.25 and 10 V/cm of the field strength. The directions of cell migrations were biased toward the cathode in a positive manner with field strength, showing galvanotactic response in a dose-dependent manner. Quantitative analysis of the relationship between field strengths and directional movements revealed that the biased movements of the cells depend on the square of electric field strength, which can be described by one simple phenomenological equation. The threshold strength for the galvanotaxis was between 0.25 and 1 V/cm. Galvanotactic efficiency reached to half-maximum at 2.6 V/cm, which corresponds to an approximate 8 mV voltage difference between the cathode and anode direction of 10 microm wide, round cells. Based on these results, possible mechanisms of galvanotaxis in Dictyostelium cells were discussed. This development of experimental system, together with its good microscopic accessibility for intracellular signaling molecules, makes Dictyostelium cells attractive as a model organism for elucidating stochastic processes in the signaling systems responsible for cell motility and its regulations.


IEEE Transactions on Electron Devices | 2011

A Dual-Channel Ferroelectric-Gate Field-Effect Transistor Enabling nand -Type Memory Characteristics

Yukihiro Kaneko; Hiroyuki Tanaka; Michihito Ueda; Yoshihisa Kato; Eiji Fujii

We demonstrate here an oxide memory (OxiM) transistor as a new type of ferroelectric-gate field-effect transistor (FeFET), provided with a dual (top and bottom) channel, which can memorize channel conductance with a dynamic range exceeding 104. This new transistor consists entirely of the following oxide-based thin films: SrRuO3 (bottom gate electrode); Pb(Zr, Ti)O3 (ferroelectric); ZnO (semiconductor); and SiON (gate insulator). A notable feature of the OxiM transistor is that two types of FET, i.e., a top gate-type thin-film transistor (top-TFT) and a bottom gate-type FeFET (bottom-FeFET), are stacked with a conduction layer of thin ZnO film in common. The channel conductance of the top-TFT and the bottom-FeFET can be controlled independently by the top gate and the bottom gate, respectively. We were successful in fabricating a nand memory circuit using serially connected OxiM transistors. The dual-gate structure allows disturb-free reading. Multivalued data can also be memorized in an OxiM transistor with a retention time of over 3.5 months.


Applied Physics Letters | 2011

A 60 nm channel length ferroelectric-gate field-effect transistor capable of fast switching and multilevel programming

Yukihiro Kaneko; Yu Nishitani; Michihito Ueda; Eisuke Tokumitsu; Eiji Fujii

We demonstrate a 60 nm channel length ferroelectric-gate field-effect transistor (FeFET) with thin-film transistor structure and good electrical properties. The FeFET contains three oxide thin-films: SrRuO3 (bottom gate electrode), Pb(Zr,Ti)O3 (ferroelectric), ZnO (semiconductor). The FeFET drain current-bottom gate voltage (IDS−VGS) characteristics show a high ON/OFF ratio of 105. The drain current ON/OFF ratio was about three orders of magnitude for write pulse widths as narrow as 10 ns. Although the channel length is set at 60 nm, the conductance can be changed continuously by varying the write pulse width. Good retention properties for three-level data were demonstrated.


Applied Physics Express | 2011

Large Transverse Piezoelectricity in Strained (Na,Bi)TiO3–BaTiO3 Epitaxial Thin Films on MgO(110)

Hideaki Adachi; Yoshiaki Tanaka; Takakiyo Harigai; Michihito Ueda; Eiji Fujii

Large transverse piezoelectricity has been demonstrated in lead-free epitaxial (Na,Bi)TiO3–BaTiO3 (NBT–BT) thin films grown on MgO(110) substrates. Through the internal strain caused by the difference in thermal expansion between NBT–BT and MgO, the crystal structure of the films was distorted to orthorhombic lattice, which does not form in bulk NBT–BT. The films showed a planar anisotropic nature where the effective transverse piezoelectricity along the orthorhombic b-axis was much larger than that along the orthorhombic a-axis. For the NBT–BT film with 9% BaTiO3, transverse piezoelectric coefficient d31* along the orthorhombic b-axis reached as high as -221 pC/N.


Journal of Applied Physics | 2011

Correlated motion dynamics of electron channels and domain walls in a ferroelectric-gate thin-film transistor consisting of a ZnO/Pb(Zr,Ti)O3 stacked structure

Yukihiro Kaneko; Yu Nishitani; Hiroyuki Tanaka; Michihito Ueda; Yoshihisa Kato; Eisuke Tokumitsu; Eiji Fujii

We studied the switching dynamics of a ferroelectric-gate thin-film transistor (FeTFT) consisting entirely of oxide-based thin films: SrRuO3 (SRO: bottom-gate electrode), Pb(Zr,Ti)O3 (PZT: ferroelectric), and ZnO (semiconductor). We switched the FeTFT channel conductance by applying short pulses to the gate electrode. We found that the switching of a FeTFT was caused by the domain wall motion in a ferroelectric film. The polarization reversal starts from the region located under the source and drain electrodes and travels along the channel length direction. In addition, the domain wall velocity increases as the domain wall gets closer to the source and drain electrodes in a ferroelectric film. Therefore, a FeTFT has the scaling merit of fast operation speed.


Applied Optics | 1998

High-efficiency diffractive micromachined chopper for infrared wavelength and its application to a pyroelectric infrared sensor

Michihito Ueda; Teruhiro Shiono; Tatsuo Ito; Kazuo Yokoyama

We have developed a diffractive micromachined chopper (DMC) for an IR wavelength of ~10 mum. This device operates mechanically by movable reflection grating beams. It modulates the diffraction efficiency by controlling the displacement of grating beams by an electrostatic force. For a CO(2) laser beam, a high modulation efficiency of 84% with an -0.8-dB small insertion loss was obtained by detecting 0th-order diffracted light. A novel pyroelectric IR microsensor with a DMC and a diffractive multilevel Si microlens was proposed and it demonstrated the detection of human existence.


Japanese Journal of Applied Physics | 2013

Dynamic Observation of Brain-Like Learning in a Ferroelectric Synapse Device

Yu Nishitani; Yukihiro Kaneko; Michihito Ueda; Eiji Fujii; Ayumu Tsujimura

A brain-like learning function was implemented in an electronic synapse device using a ferroelectric-gate field effect transistor (FeFET). The FeFET was a bottom-gate type FET with a ZnO channel and a ferroelectric Pb(Zr,Ti)O3 (PZT) gate insulator. The synaptic weight, which is represented by the channel conductance of the FeFET, is updated by applying a gate voltage through a change in the ferroelectric polarization in the PZT. A learning function based on the symmetric spike-timing dependent synaptic plasticity was implemented in the synapse device using the multilevel weight update by applying a pulse gate voltage. The dynamic weighting and learning behavior in the synapse device was observed as a change in the membrane potential in a spiking neuron circuit.


Japanese Journal of Applied Physics | 2006

Stochastic Computing Chip for Measurement of Manhattan Distance

Michihiro Hori; Michihito Ueda; Atsushi Iwata

We have proposed a stochastic computing system utilizing arbitrary chaos generators as random signal generators. The system can execute linear and nonlinear computations using the representation of analog quantities by pulse densities with random signals. In the case that a very high accuracy of computation is not required, the stochastic computing system can be implemented efficiently using future scaled complementary metal oxide semiconductor (CMOS) devices and has the programmability of computation time and accuracy without changing hardware. We designed a 0.35 µm CMOS stochastic computing chip for the parallel measurement of Manhattan distance using tent chaos generators, exclusive OR (EXOR) circuits, and two types of summation circuit with analog charge integration and digital pulse counting. By an experiment using a fabricated test chip, we confirmed the operation and accuracy of the stochastic computing chip.

Collaboration


Dive into the Michihito Ueda's collaboration.

Top Co-Authors

Avatar

Yukihiro Kaneko

Tokyo Institute of Technology

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Researchain Logo
Decentralizing Knowledge