Yuan-Hao Huang

A Hybrid RF/Baseband Precoding Processor Based on Parallel-Index-Selection Matrix-Inversion-Bypass Simultaneous Orthogonal Matching Pursuit for Millimeter Wave MIMO Systems

A millimeter wave (mm-wave) communication system provides multi-Gb/s data rates in short-distance transmission. Because millimeter waves have short wavelength, transceivers can be composed of large antenna arrays to alleviate severe signal attenuation. Furthermore, the link performance can be improved by adopting precoding technology in multiple data stream transmission. However, the complexity of radio frequency (RF) chains increases when large antenna arrays are used in mm-wave systems. To reduce the hardware cost, the precoding circuit can be jointly designed in both analog and digital domains to reduce the required number of RF chains. This paper proposes a new method of building the joint RF and baseband precoder that reduces the computation complexity of the original precoder reconstruction algorithm and enables highly parallel hardware architecture. Moreover, the proposed precoder reconstruction algorithm was designed and implemented using TSMC 90-nm UTM CMOS technology. The proposed precoder reconstruction processor supports the transmissions of one to four data streams for 8 × 8 mm-wave multiple-input multiple-output systems. The operating frequency of this chip was 167 MHz, and the power consumption was 243.2 mW when the supply voltage was 1 V. The core area of the postlayout result was about 3.94 mm 2. The proposed processor achieved 4, 4.9, 6.7, and 6.7 M channel matrices per second in four-, three-, two-, and one-stream modes, respectively.

Interpolation-Based QR Decomposition and Channel Estimation Processor for MIMO-OFDM System

This paper presents a modified interpolation-based QR decomposition algorithm for the grouped-ordering multiple input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) systems. Based on the original research that integrates the calculations of the frequency-domain channel estimation and the QR decomposition for the MIMO-OFDM system, this study proposes a modified algorithm that possesses a scalable property to save the power consumption for interpolation-based QR decomposition in the variable-rank MIMO scheme. Furthermore, we also develop the general equations and a timing scheduling method for the hardware design of the proposed QR decomposition processor for the higher-dimension MIMO system. Based on the pro posed algorithm, a configurable interpolation-based QR decomposition and channel estimation processor was designed and implemented using a 90-nm one-poly nine-metal CMOS technology. The processor supports 2 × 2, 2 × 4 and 4 × 4 QR-based MIMO detection for the 3GPP-LTE MIMO-OFDM system and achieves the throughput of 35.16 MQRD/s at its maximum clock rate 140.65 MHz.

Energy-Saving Cooperative Spectrum Sensing Processor for Cognitive Radio System

Cooperative spectrum sensing has recently become an important research topic for cognitive radio systems because it solves the hidden terminal problem in single-user spectrum sensing. However, idle cognitive users must consume massive spectrum sensing energy for one operating cognitive user. This characteristic reduces the attraction of the cooperative spectrum sensing technique in practical cognitive radio systems. Therefore, this paper develops a partial spectrum sensing algorithm with decision result prediction (DRP) and decision result modification (DRM) techniques to reduce the cooperative spectrum sensing energy. This study also designs and implements an energy-saving spectrum sensing processor for cognitive radio systems. The proposed cooperative spectrum sensing chip reduces energy consumption by about 64% for one fast Fourier transform (FFT) spectrum sensing calculation. For any given specified spectrum detection time, the proposed chip could also improve the detection performance compared to the traditional FFT spectrum sensing.

High-Efficiency Soft-Error-Tolerant Digital Signal Processing Using Fine-Grain Subword-Detection Processing

The soft error problem in digital circuits is becoming increasingly important as the IC fabrication technology progresses from the deep submicrometer scale to the nanometer scale. This paper proposes a subword-detection processing (SDP) technique and a fine-grain soft-error-tolerance (FGSET) architecture to improve the performance of the digital signal processing circuit. In the SDP technique, the logic masking property of the soft error in the combinational circuit is utilized to mask the single-event upset (SEU) caused by disturbing particles in the inactive area. To further improve the performance, the masked portion of the datapath can be used as the estimation redundancy in the algorithmic softerror-tolerance (ASET) technique. This technique is called subword-detection and redundant processing (SDRP). In the FGSET architecture, the soft error in each processing element (fine grain) can be recovered by the arithmetic datapath-level ASET technique. Analysis of the fast Fourier transform processor example shows that the proposed FGSET architecture can improve the performance of the coarse-grain SET (CGSET) by 8.5 dB. The low-cost SDP technique (1.03x) yields a noise reduction of 5.3 dB over the CGSET approach (1.40x), while the efficient SDRP I (1.57x) and SDRP II (1.88x) techniques outperform the CGSET approach by 24.5 and 30.5 dB, respectively.

Design of an OFDM receiver for high-speed wireless LAN

In this paper, we propose a baseband OFDM receiver for highspeed wireless local area network defined in IEEE 802.11a physical layer. Algorithms for channel estimation/equalization, timing recovery, carrier frequency acquisition/tracking, and sampling clock tracking are individually designed and later integrated into a receiver architecture. Simulation results show that the proposed OFDM receiver architecture is capable of high-rate data transmission in indoor multi-path fading channels.

A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications

This work proposes a communication digital signal processor (DSP) suitable for massive signal processing operations in orthogonal frequency division multiplexing (OFDM) and code-division multiple-access (CDMA) communication systems. The OFDM-based IEEE 802.11a wireless LAN transceiver and CDMA-based WCDMA uplink receiver are simulated to evaluate the computation requirements of future communication systems. The architecture of the communication digital signal processor is established according to the computational complexity of these simulations. The proposed architecture supports basic butterfly operations, single/double-precision and real- and complex-valued multiplication-and-accumulation (MAC), squared error computation, and add-compare-select (ACS) operation. This butterfly/complex MAC architecture can greatly enhance the execution efficiency of operations often found in communication applications. The processor chip is fabricated using a 0.35-/spl mu/m n-well one-poly four-metal CMOS technology. The fabricated DSP chip reaches a speed of 1.1 G MAC/s when operating in the high-speed mode, and it achieves 4 M MAC/s/mW in the low-power mode.

An Improved Ordered-Block MMSE Detector for Generalized Spatial Modulation

In this letter, an improved ordered-block minimum-mean-squared-error (OB-MMSE) detector for generalized spatial modulation systems is presented. We first propose to use the concentrated distance metric derived from the conditional maximum likelihood estimator as the ordering metric for the OB-MMSE and then design a computationally-efficient algorithm for computing this metric. The improved ordering performance of the proposed algorithm allows the early-termination of the OB-MMSE detector without noticeable performance loss which can be exploited to further reduce its complexity. Simulation results show that the proposed algorithm can achieve better performance-complexity tradeoff compared to the existing OB-MMSE detector.

A Low-Complexity Viterbi Decoder for Space-Time Trellis Codes

Space-time trellis code (STTC) has been widely applied to coded multiple-input multiple-output (MIMO) systems because of its gains in coding and diversity; however, its great decoding complexity makes it less promising in chip realization compared to the space-time block code (STBC). The complexity of STTC decoding lies in the branch metric calculation in the Viterbi algorithm and increases significantly along with the number of antennas and the modulation order. Consequently, a low-complexity algorithm to mitigate the computational burden is proposed. The results show that more than 70%, 78%, and 83% of the computational complexity is reduced for 2 × 2, 3 × 3, and 4 × 4 MIMO configurations, respectively. Based on the proposed algorithm, a reconfigurable MISO STTC Viterbi decoder is designed and implemented using 0.18 ¿m 1P6M CMOS technology. The decoder achieves 11.14 Mbps, 8.36 Mbps, and 5.75 Mbps for 4-PSK, 8-PSK, and 16-QAM modulations, respectively.

A new audio coding scheme using a forward masking model and perceptually weighted vector quantization

This paper presents a new audio coder that includes two techniques to improve the sound quality of the audio coding system. First, a forward masking model is proposed. This model exploits adaptation of the peripheral sensory and neural elements in the auditory system, which is often deemed as the cause of forward masking. In the proposed audio coder, the forward masking is first modeled by a nonlinear analog circuit and then difference equations for finding the solution of this circuit are formulated. The parameters of the circuit are derived from several factors, including time difference between masker and maskee, masker level, masker frequency, and masker duration. Inclusion of this model in the coding process will remove more redundancy inaudible to humans and thus improves the coding efficiency. Secondly, we propose a new vector quantization technique, whose codebooks are generated by a perceptually weighted binary-tree self-organizing feature maps (PW-BTSOFM) algorithm. This vector quantization technique adopts a perceptually weighted error criterion to train and select codewords so that the quantization error is kept below the just-noticed distortion (JND) while using the smallest possible codebook, again reducing the required coded bit rate. Experimental objective and subjective sound quality measurements show that the proposed audio coding scheme requires about 30% less bits than the MPEG layer III audio coding standard.

A modified sorted-QR decomposition algorithm for parallel processing in MIMO detection

This paper proposes a modified sorted-QR decomposition algorithm for the high-dimensional multiple-input multiple-output (MIMO) detection. Due to the growing demands of high-dimension MIMO channels and large number of OFDM subcarriers, the sorted-QR decomposition becomes one of the computational bottlenecks in the QR-based MIMO detection. The proposed Givens-Rotation-based algorithm aims to improve the throughput and the hardware utilization efficiency by relaxing the sorting condition and allowing the cross-column parallel rotation operations. The simulation results show that our proposed parallel algorithm can significantly reduce the minimal computation latency from 28% to 21% of the original algorithm, and the hardware utilization rate can be enhanced from 71% to 90% for 16×16 MIMO using four Given-Rotation processing elements. The detection performance degradation is negligible and better hardware efficiency can be obtained for the larger number of MIMO antennas.