Yuang Zhang

Towards hierarchical cluster based cache coherence for large-scale network-on-chip

We introduce a novel hierarchical cluster based cache coherence scheme for large-scale NoC based distributed memory architectures. We describe the hierarchical memory organization. We show analytically that the proposed scheme has better performance than traditional counterparts both in memory overhead and communication cost.

A power-aware adaptive routing scheme for network on a chip

NoC (Network on a chip) is being proposed as a scalable and reusable communication platform for future SoC (System on a chip) applications. Power is a critical issue in interconnection network design, driven by power-related design constraints, such as power distribution optimization and thermal protection design, especially when network becomes huge. In this work, we present an on-chip routing scheme based on a new power model and dynamic XY routing algorithm, which can adapt routing decision based on power conditions, optimize power distribution and avoid hotspots occurring in the network. To verify the routing scheme, a SystemC-based NoC(Mesh4times4) simulator is built. Experiments demonstrate the proposed routing scheme can effectively regulate network power distribution to meet power balance requirement (maximum and variance of power can decrease by 8.1% and 21.1% at best respectively) with negligible network performance penalty.

Memory Architecture and Management in an NoC Platform

The memory organization and the management of the memory space is a critical part of every NoC based platform design. We propose a Data Management Engine (DME), that is a block of programmable hardware and part of every processing element. It off-loads the processing element (CPU, DSP, etc.) by managing the memory space, memory access and the communication over the on-chip network. The DME’s main functions are virtual address translation, private and shared memory management, cache coherence protocol, support for memory consistency models, synchronization and protection mechanisms for shared memory communication. The DME is fully programmable and configurable thus allowing for customized support for high level data management functions such as dynamic memory allocation and abstract data types. This chapter describes the main concepts, design and functionality of the DME and presents case studies illustrating its usage and performance.

Performance and power consumption analysis of memory efficient 3D network-on-chip architecture

With the rapid development of the technology of 3D IC and Network-on-Chip (NoC) technology, 3D NoC emerged and drew more and more attention of researchers in recent years. But the issues of memory organization and power consumption have become two great challenges in the design of 3D NoC. This paper proposed three kinds of memory efficient 3D NoC architecture called core, corner and windows in order to achieve better performance and lower power consumption for the system. A simulation platform of 3D NoC is built with a systematical modeling language -SystemC to evaluate the performance. The experiment result shows that when compared with other two traditional 3D NoC memory architecture perlayer and mixed, two 3D NoC architectures we proposed can gain better performance and lower power consumption respectively.

Performance and Network Power Evaluation of Tightly Mixed SRAM NUCA for 3D Multi-core Network on Chips

Last level cache (LLC) is crucial for the performance of chip multiprocessors (CMPs), while power is a significant design concern for 3D CMPs. In this paper, we focus on the SRAM-based Non-Uniform Cache Architecture (NUCA) for 3D Multi-core Network-on-Chip (McNoC) systems. A tightly mixed SRAM NUCA for 3D mesh NoC is presented and analyzed. We evaluate the performance and network power with benchmarks based on a full system simulation framework. Experiment results on 16-core 3D NoC systems show that the tightly mixed NUCA could provide up to 31.71% and on average 5.95% performance improvement compared to a base 3D NUCA scheme. The tightly mixed 3D NUCA NoC can reduce network power consumption in 1.07%-15.74% and 9.64% on average compared to a baseline 3D NoCs. Our analysis and experimental results provide a guideline to design efficient 3D NoCs with stacking NUCA.

Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC

In the design of 3D Network-on-chip, performance of the router is so important that it directly impacts the capability of 3D NoC. Considering the advantages and disadvantages of packet switching and circuit switching, this paper presents a mass message transmission aware buffer-less router for 3D NoC based on packet-circuit switching, which has the advantage of low buffer consumption and short transmission delay. That makes it suitable for mass message transmission on 3D NoC. We synthesize our mass message transmission aware buffer-less Packet-Circuit Switching Router for 3D NoC with XILINX 12.2. The device type is xc6vlx550t. The router can achieve a max frequency of 353.526 MHz, while the throughput of every channel is 16 Gbps.

Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links

Through Silicon Vias (TSVs) based 3D Network on Chip (NoC) is a promising communication platform solution for future multicore systems. Due to the cost in terms of yield, chip area and design complexity, minimizing the number of TSVs in 3D integrated circuits has become an important design issue. In this paper, we present the circuit design of the proposed lateral asynchronous and vertical synchronous (LAVS) 3D NoC with double pumped vertical links and evaluate the area overhead, the die cost and the network performance of the scheme. Experiment shows the proposed scheme reduces overall router silicon area by 39.8%, and reduces the die cost by 20% for 3D NoC with 64 nodes each layer, and improves the ratio between performance and area by 16.8%.

Exploring stacked main memory architecture for 3D GPGPUs

The tremendous number of threads on general purpose graphic processing units (GPGPUs) poses significant challenges on memory architecture design. 3D stacked main memory architecture atop GPGPU is a potential approach to provide high data communication bandwidth and low access latency to meet the requirement of GPGPUs. In this paper, we explore the performance of 3D GPGPUs with stacked main memory. The experimental results show that the 3D stacked GPGPU can provide up to 124.1% and on average 55.8% performance improvement compared to a 2D GPGPU scheme.

A SystemC-based hardware platform design of Network-on-a-Chip

As the rapid development of semiconductor technology, more and more processor cores and large reusable components have been integrated on a single silicon die. And the rapid increase of requirement from applications is leading to the exploration of even more innovative architectures for complex SoC. Network-on-a-Chip (NoC) is a key example to meet this trend. A SystemC-based hardware platform design of NoC with 2D-Mesh architecture is introduced in this paper. The router module and network interface module of the NoC are described in detail. And experiments demonstrated that this NoC hardware platform can work well.