Shuzhuan He

Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm

Three dimensional network-on-chip (3D NoC) has been suggested as a potential alternative to solve insurmountable problems in 2D field such as global wire length and packet latency for many years. And the mapping problem plays an import role in 3D NoC design which will have a great influence on overall system performance. In this paper, we mainly focus on the latency-aware mapping for 3D NoC. Differing from the conventional mapping algorithms, the packet latency under no congestion and congestion are both taken into account. Since more than one metrics are considered in this situation, instead of the traditional single-objective genetic algorithm, a rank-based multi-objective genetic algorithm (RMGA) is adopted in our work to explore the optimal approximation of the Pareto-front efficiently and accurately. To evaluate the proposed algorithm, the video object plane decoder (VOPD) is used as a case study. The results show that the RMGA can obtain the approximate Pareto-front well and compared with the best results chosen from random generated solutions, the RMGA can achieve an improvement of 24.4% and 15.4% for latency metrics under no congestion and congestion respectively.

A high precision CMOS bandgap reference with second-order curvature-compensation

A high precision bandgap reference circuit with second-order curvature-compensation to improve the temperature coefficient in wider temperature range is presented in this paper. Simulation results with CSMC 0.6 mum 2P2M CMOS process model show that, the design features a reference voltage of 1.255 V at 25degC. The temperature coefficient is less than 5.29 ppm/degC at the range of -35-120 degC. With supply voltage variation of 2-5 V, the line-regulation ratio is 110 muV/V And PSRR is -81.54 dB. The active area of layout is 300 mum times 400 mum. Test results based on 20 samples show a good agreement with the simulation results.

Performance and power consumption analysis of memory efficient 3D network-on-chip architecture

With the rapid development of the technology of 3D IC and Network-on-Chip (NoC) technology, 3D NoC emerged and drew more and more attention of researchers in recent years. But the issues of memory organization and power consumption have become two great challenges in the design of 3D NoC. This paper proposed three kinds of memory efficient 3D NoC architecture called core, corner and windows in order to achieve better performance and lower power consumption for the system. A simulation platform of 3D NoC is built with a systematical modeling language -SystemC to evaluate the performance. The experiment result shows that when compared with other two traditional 3D NoC memory architecture perlayer and mixed, two 3D NoC architectures we proposed can gain better performance and lower power consumption respectively.

Monolithic H-bridge brushless DC vibration motor driver with a highly sensitive hall sensor in 0.18 μm complementary metal-oxide semiconductor technology

A monolithic low-voltage H-bridge brushless DC (BLDC) vibration motor driver with an integrated high sensitivity Hall sensor has been presented in 0.18 μm high-voltage complementary metal-oxide semiconductor technology. To improve the motor start-up reliability, a full-on start mode is applied to realise a high-speed start sequence by shortening the start-up time. Meanwhile, an active start function is activated to prevent dead point phenomenon if the motor magnet pole sensed by the built-in Hall sensor does not change during the motor starting. This complete one-chip solution for driving the BLDC vibration motors provides significantly enhanced reliabilities, including thermal shutdown and under voltage lockout protection functions, and fully eliminates the need for any external components. The measured results show that the motor driver chip has a typical operating point of 2 mT and a typical releasing point of - 2 mT, showing a hysteresis magnetic property of 4 mT. The chip is very robust. It can operate well within a low supply voltage range of 2-4 V and can output a maximum of 300 mA peak current while the ambient temperature ranges from - 40 to 85°C.

Single-Chip Integrated 3-D Hall Sensor

A single-chip three-dimensional(3-D)Hall sensor for high-accuracy three-axis magnetic-field measurements is presented. The chip contains a 3-D Hall device, the analog signal conditioning circuit, an A/D converter and the digital signal-processing unit. The 3-D Hall device contains horizontal and vertical Hall elements. The horizontal Hall element measures the perpendicular component, and four vertical Hall elements measure the two in-plane components of a magnetic flux. With the detailed analysis of the essential factors affecting Hall voltage, the signal conditioning circuit based on spinning current technique is provided, which works in 100kHz and can cancel the offset, reduce the 1/f noise and amplify the signal. The digital signal-processing unit provides the high-accuracy mapping algorithm between measured values and target values.

A Mask-Misalignment Offset Reduction Method for Design of Cross-Like CMOS Hall Devices

The mask-misalignment offset, as an inevitable part of the initial offset, is necessary to be reduced in the design of cross-like Hall devices. In this paper, a method is proposed to reduce the mask-misalignment offset. In order to find the method to reduce the mask-misalignment offset, the Hall sensors of different sizes and with different N-type doping regions are simulated by Silvaco Technology Computer Aided Design simulator. The Hall devices of different sizes have the same ratio of length and width, making the geometrical factor unchanged. The two different N-type doping regions are extracted from the 0.18 μm BCDlite™ technology provided by GLOBALFOUNDRIES. We found out the effects of different sizes and different N-type doping active regions on the offset.

Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC

In the design of 3D Network-on-chip, performance of the router is so important that it directly impacts the capability of 3D NoC. Considering the advantages and disadvantages of packet switching and circuit switching, this paper presents a mass message transmission aware buffer-less router for 3D NoC based on packet-circuit switching, which has the advantage of low buffer consumption and short transmission delay. That makes it suitable for mass message transmission on 3D NoC. We synthesize our mass message transmission aware buffer-less Packet-Circuit Switching Router for 3D NoC with XILINX 12.2. The device type is xc6vlx550t. The router can achieve a max frequency of 353.526 MHz, while the throughput of every channel is 16 Gbps.

High Sensitivity Horizontal Hall Sensors in 0.35 um BCD Technology

In this paper, we designed a group of horizontal Hall sensors in 0.35 μm BCD (bipolar/CMOS/DMOS) technology. Compared with the existing Hall devices, the design has improvement in parts such as Hall cell parameter set and layout design under BCD technology. And then the Hall chip is taped out. The results from the precise experiment of the Hall cell verify the optimization method which can be used to realize Hall sensitivity of 964 V/ (AT).

A SystemC-based hardware platform design of Network-on-a-Chip

As the rapid development of semiconductor technology, more and more processor cores and large reusable components have been integrated on a single silicon die. And the rapid increase of requirement from applications is leading to the exploration of even more innovative architectures for complex SoC. Network-on-a-Chip (NoC) is a key example to meet this trend. A SystemC-based hardware platform design of NoC with 2D-Mesh architecture is introduced in this paper. The router module and network interface module of the NoC are described in detail. And experiments demonstrated that this NoC hardware platform can work well.