Yuanqi Hu

A Robust ISFET pH-Measuring Front-End for Chemical Reaction Monitoring

This paper presents a robust, low-power and compact ion-sensitive field-effect transistor (ISFET) sensing front-end for pH reaction monitoring using unmodified CMOS. Robustness is achieved by overcoming problems of DC offset due to trapped charge and transcoductance reduction due to capacitive division, which commonly exist with implementation of ISFETs in CMOS. Through direct feedback to the floating gate and a low-leakage switching scheme, all the unwanted factors are eliminated while the output is capable of tracking a pH reaction which occurs at the sensing surface. This is confirmed through measured results of multiple devices of different sensing areas, achieving a mean amplification of 1.28 over all fabricated devices and pH sensitivity of 42.1 mV/pH. The front-end is also capable of compensating for accumulated drift using the designed switching scheme by resetting the floating gate voltage. The circuit has been implemented in a commercially-available 0.35 μm CMOS technology achieving a combined chemical and electrical output RMS noise of 3.1 mV at a power consumption of 848.1 nW which is capable of detecting pH changes as small as 0.06 pH.

A direct-capacitive feedback ISFET interface for pH reaction monitoring

In this paper we propose a low-power, compact ISFET interface capable of overcoming problems of DC offset due to trapped charge and transcoductance reduction due to capacitive division, which commonly exist with implementation in CMOS. Through direct feedback to the floating gate and a low-leakage switching scheme, all the unwanted factors are eliminated while the output is capable of tracking a pH reaction which occurs at the sensing surface. The circuit has been designed to be an inherently constant-voltage-constant-current structure, avoiding any loss of sensitivity due to capacitive division. Additionally, a tradeoff between noise and stability is presented for optimum choice of capacitors. The proposed ISFET and interface has been designed in a typical 0.35 μm process, has an area 60 ×70um2 and consumes 231nW of power, which facilitates its implementation for large chemical sensing arrays.

An Automatic Gain Control System for ISFET Array Compensation

This paper presents an automatic gain calibration system for ion-sensitive field effect transistors (ISFETs) sensing arrays which compensates for mismatch in the gain of the pixels. The system utilizes the high frequency spectrum of the sensed signal to superimpose a reference sine wave through the reference electrode, which allows identification and calibration of the local gain. The complete system has been fabricated in a 0.35 μm CMOS process and has been designed to achieve very high accuracy and a small settling time to allow fast pixel switching. Measured results confirm good performance with only a 1.15% deviation in gain caused by noise and harmonic distortion and a rapid settling time of 70.5 μs which is suitable for CMOS-based ISFET arrays.

A SAR based calibration scheme for ISFET sensing arrays

This paper presents an automatic calibration system for ISFET chemical sensing arrays to tune out any mismatch in sensitivity. Through exploitation of the high frequency spectrum of the sensed signal which does not contain any chemical reaction information, local sensitivity is examined and then calibrated through a successive approximation control mechanism and an 8-bit variable gain amplifier to provide high accuracy tuning. The total calibration process contains three phases, peak detection, AGC through a SAR and finally sensor readout of the detected chemical signal. Designed in a typical 0.35μm CMOS process, the system is capable of compensating a sensitivity deviation of up to 24% in an ISFET array, constraining the error to just 1.5%.

A CMOS architecture allowing parallel DNA comparison for on-chip assembly

This paper introduces a CMOS based system that has been designed to allow parallel comparison of fragmented DNA sequences for on-chip assembly. The compatibility of different existing PC-based algorithms for implementation in CMOS is compared and the overlap-layout-consensus approach is found to be the most suitable one. The designed system comprises a scalable processing array capable of parallel computation, which allows identification of overlaps in DNA fragments in addition to error tolerance through dynamic programming. Analysis shows that there is a “pixel area vs computation time” trade-off when implementing such a parallel architecture. Results from a hypothetical assembly confirm good overlap detection and error tolerance, with up to 94% similarity in the detected overlaps, when the error is as much as 10%.

A 5s-time-constant temperature-stable integrator for a tuneable PID controller in LOC applications

In this paper, we present a novel, ultra-long-time-constant analogue integrator for a PID controller in Lab-on-Chip (LOC) applications. A time constant of up to 5 seconds is achievable using a capacitance of only 18pF by exploiting transconductance reduction techniques involving current splitting and gm-attenuated OTA. Additionally, this architecture provides the ability to digitally tune the time constant from 200ms to 5s with 4-bit programmability. The design achieves a temperature dependance of 1.2% over the range from 0°C to 100°C with micropower consumption.

An ion imaging ISFET array for Potassium and Sodium detection

In this paper, we present a novel approach to ISFET arrays which allows the conception of ion imaging Lab-on-CMOS platforms. K+ and Na+ selective polymer membranes are deposited on the surface of the array so that each pixel is selective to a particular ionic species. An initial calibration produces an accurate mapping of the array in terms of ion-selective regions and determines the sensitivity of the membrane. The system exhibits K+ and Na+ sensitivities of respectively 51.2 mV/dec and 46.8 mV/dec, and demonstrates good discrimination of Potassium and Sodium ions for a common solution exposed to the chip, with a reported error lower than 1%. This ISFET-based tri-ion imaging array constitutes the basis for a portable integrated multi-ion platform.

A Real-Time de novo DNA Sequencing Assembly Platform Based on an FPGA Implementation

This paper presents an FPGA based DNA comparison platform which can be run concurrently with the sensing phase of DNA sequencing and shortens the overall time needed for de novo DNA assembly. A hybrid overlap searching algorithm is applied which is scalable and can deal with incremental detection of new bases. To handle the incomplete data set which gradually increases during sequencing time, all-against-all comparisons are broken down into successive window-against-window comparison phases and executed using a novel dynamic suffix comparison algorithm combined with a partitioned dynamic programming method. The complete system has been designed to facilitate parallel processing in hardware, which allows real-time comparison and full scalability as well as a decrease in the number of computations required. A base pair comparison rate of 51.2 G/s is achieved when implemented on an FPGA with successful DNA comparison when using data sets from real genomes.

Live demonstration: Real-time chemical imaging of ionic solutions using an ISFET array

We demonstrate a CMOS-based lab-on-chip platform which is capable of ion imaging to detect a variation in hydrogen, potassium and sodium ions. An ISFET array is used to detect a change in ion concentration with a calibration scheme to cancel the offset due to trapped charge. The SÍ3N4 passivation layer confers an inherent sensitivity to the sensors, and additional polymer membranes are pipetted containing a potassium and sodium ionophore. An initial algorithm identifies the sensitivity of each pixel towards the target ions. The user can inject a solution with a given concentration of ions and observe the real-time output change of the array on a MATLAB interface. The display then provides an estimate of the target ion concentration.

A study of the partitioned dynamic programming algorithm for genome comparison in FPGA

This paper explores the potential of partitioning the dynamic programming algorithm to utilise the capabilities of FPGA platforms for parallel genome sequence comparison and assembly. We use this to solve the prefix-suffix approximate matching problem to find overlaps between DNA strands in a given sequence. This is achieved by partitioning the basic dynamic programming (DP) algorithm into a series of discrete sub-DP calculations. Analysis of the error rate as a result of this partitioning by applying random sequences as input data is shown, and simulation results confirm good matching with the original algorithm with an error of less that 1.5% in the worst case. Optimisation for array implementation in FPGA is shown and linear scalability for larger arrays is proven. Simulation results of the whole system confirm 98.8% similarity of the overlap adjacent matrix between error and error-free data.