Timothy G. Constandinou

Wireless Capsule Endoscope for Targeted Drug Delivery: Mechanics and Design Considerations

This paper describes a platform to achieve targeted drug delivery in the next-generation wireless capsule endoscopy. The platform consists of two highly novel subsystems: one is a micropositioning mechanism which can deliver 1 ml of targeted medication and the other is a holding mechanism, which gives the functionality of resisting peristalsis. The micropositioning mechanism allows a needle to be positioned within a 22.5° segment of a cylindrical capsule and be extendible by up to 1.5 mm outside the capsule body. The mechanism achieves both these functions using only a single micromotor and occupying a total volume of just 200 mm3. The holding mechanism can be deployed diametrically opposite the needle in 1.8 s and occupies a volume of just 270 mm3. An in-depth analysis of the mechanics is presented and an overview of the requirements necessary to realize a total system integration is discussed. It is envisaged that the targeted drug delivery platform will empower a new breed of capsule microrobots for therapy in addition to diagnostics for pathologies such as ulcerative colitis and small intestinal Crohns disease.

A Partial-Current-Steering Biphasic Stimulation Driver for Vestibular Prostheses

This paper describes a novel partial-current-steering stimulation circuit for implantable vestibular prostheses. The drive hardware momentarily delivers a charge-balanced asymmetric stimulus to a dummy load before steering towards the stimulation electrodes. In this fashion, power is conserved while still gaining from the benefits of current steering. The circuit has been designed to be digitally programmable as part of an implantable vestibular prosthesis. The hardware has been implemented in AMS 0.35 mum 2P4M CMOS technology.

An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis

This paper presents an 8 channel energy-efficient neural stimulator for generating charge-balanced asymmetric pulses. Power consumption is reduced by implementing a fully-integrated DC-DC converter that uses a reconfigurable switched capacitor topology to provide 4 output voltages for Dynamic Voltage Scaling (DVS). DC conversion efficiencies of up to 82% are achieved using integrated capacitances of under 1 nF and the DVS approach offers power savings of up to 50% compared to the front end of a typical current controlled neural stimulator. A novel charge balancing method is implemented which has a low level of accuracy on a single pulse and a much higher accuracy over a series of pulses. The method used is robust to process and component variation and does not require any initial or ongoing calibration. Measured results indicate that the charge imbalance is typically between 0.05%-0.15% of charge injected for a series of pulses. Ex-vivo experiments demonstrate the viability in using this circuit for neural activation. The circuit has been implemented in a commercially-available 0.18 μm HV CMOS technology and occupies a core die area of approximately 2.8 mm2 for an 8 channel implementation.

Feature Extraction using First and Second Derivative Extrema (FSDE), for Real-time and Hardware-Efficient Spike Sorting

Next generation neural interfaces aspire to achieve real-time multi-channel systems by integrating spike sorting on chip to overcome limitations in communication channel capacity. The feasibility of this approach relies on developing highly efficient algorithms for feature extraction and clustering with the potential of low-power hardware implementation. We are proposing a feature extraction method, not requiring any calibration, based on first and second derivative features of the spike waveform. The accuracy and computational complexity of the proposed method are quantified and compared against commonly used feature extraction methods, through simulation across four datasets (with different single units) at multiple noise levels (ranging from 5 to 20% of the signal amplitude). The average classification error is shown to be below 7% with a computational complexity of 2N-3, where N is the number of sample points of each spike. Overall, this method presents a good trade-off between accuracy and computational complexity and is thus particularly well-suited for hardware-efficient implementation.

A multichannel DNA SoC for rapid point-of-care gene detection

Point-of-care diagnostics for detection of genetic sequences require biosensing platforms that are sensitive to the target sequence, and are also fast, mass-manufacturable, and - ideally - disposable. Conventional lab-based methods of detecting DNA sequences rely on optical methods, typically by the addition of fluorescent tags to the target DNA that in turn latches onto a DNA probe sequence only if there is a match between the two. These techniques are cumbersome as they require upfront tagging of the DNA with expensive reagents and laboratory equipment to detect the optical signals. Recently, developments have been made in transferring these optical methods to inexpensive CMOS ICs [1], although the requirement for tagging remains. Magnetic beads offer an alternative means of tagging the DNA and their presence can be detected by the shift in resonant frequency of an on-chip LC tank [2]. There have also been attempts based on “label-free” electrochemical detection using FETs [3,4], but none of these have been implemented in unmodified standard CMOS.

An Analogue Front-End Model for Developing Neural Spike Sorting Systems

In spike sorting systems, front-end electronics is a crucial pre-processing step that not only has a direct impact on detection and sorting accuracy, but also on power and silicon area. In this work, a behavioural front-end model is proposed to assess the impact of the design parameters (including signal-to-noise ratio, filter type/order, bandwidth, converter resolution/rate) on subsequent spike processing. Initial validation of the model is provided by applying a test stimulus to a hardware platform and comparing the measured circuit response to the expected from the behavioural model. Our model is then used to demonstrate the effect of the Analogue Front-End (AFE) on subsequent spike processing by testing established spike detection and sorting methods on a selection of systems reported in the literature. It is revealed that although these designs have a wide variation in design parameters (and thus also circuit complexity), the ultimate impact on spike processing performance is relatively low (10-15%). This can be used to inform the design of future systems to have an efficient AFE whilst also maintaining good processing performance.

A CMOS-Based ISFET Chemical Imager With Auto-Calibration Capability

This paper presents a novel auto-calibration technique for eliminating sensor mismatch in CMOS-based chemical imagers. Designed using an 8 × 8 array comprising of pH-sensitive ion-sensitive field-effect transistors (ISFETs), the chemical imager is capable of implementing a gradient-based calibration algorithm by biasing programmable-gate (PG) ISFETs at a common operating point when exposed to a solution of homogenous pH. The system was fabricated in a typical 0.35-μm CMOS technology and demonstrated a fast rate of convergence (500 ms per iteration) while a convergence accuracy of 45 mV on a gain of 10 (0.5% relative standard error and 2% pixel-to-pixel variation) was achieved. A maximum pH sensitivity of 57 mV/pH is also reported.

A micropower centroiding vision processor

A biologically-inspired hybrid vision chip is presented for real-time object-based processing for tasks such as centroiding, sizing and counting of enclosed objects. This system presents the first silicon retina capable of centroiding and sizing multiple objects in true parallel fashion. Based on a novel distributed algorithm, this approach uses the input image to enclose a feedback loop to realize a data-driven pulsating action. The sensor provides a resolution of 48 /spl times/ 48 pixels with a 85 /spl mu/m/spl times/85 /spl mu/m pixel footprint and has been measured to consume 243 /spl mu/W at 1.8-V supply, achieving an equivalent computational efficiency of 724.64 MIPS/mW with a 500-/spl mu/s process time.

Minimum requirements for accurate and efficient real-time on-chip spike sorting.

BACKGROUND Extracellular recordings are performed by inserting electrodes in the brain, relaying the signals to external power-demanding devices, where spikes are detected and sorted in order to identify the firing activity of different putative neurons. A main caveat of these recordings is the necessity of wires passing through the scalp and skin in order to connect intracortical electrodes to external amplifiers. The aim of this paper is to evaluate the feasibility of an implantable platform (i.e., a chip) with the capability to wirelessly transmit the neural signals and perform real-time on-site spike sorting. NEW METHOD We computationally modelled a two-stage implementation for online, robust, and efficient spike sorting. In the first stage, spikes are detected on-chip and streamed to an external computer where mean templates are created and sent back to the chip. In the second stage, spikes are sorted in real-time through template matching. RESULTS We evaluated this procedure using realistic simulations of extracellular recordings and describe a set of specifications that optimise performance while keeping to a minimum the signal requirements and the complexity of the calculations. COMPARISON WITH EXISTING METHODS A key bottleneck for the development of long-term BMIs is to find an inexpensive method for real-time spike sorting. Here, we simulated a solution to this problem that uses both offline and online processing of the data. CONCLUSIONS Hardware implementations of this method therefore enable low-power long-term wireless transmission of multiple site extracellular recordings, with application to wireless BMIs or closed-loop stimulation designs.

Exploiting CMOS Technology to Enhance the Performance of ISFET Sensors

This letter presents a novel method for fabricating ion-sensitive field-effect transistor (ISFET) devices in unmodified CMOS technologies. Conventional CMOS ISFETs utilize the protective passivation coating as the sensing membrane, with the sensed potential being coupled down to the floating MOS gate via a stack of conducting and insulating layers. The proposed structure minimizes the use of these layers by exploiting the passivation-opening mask, normally intended for bond-pad openings. Parasitic effects such as reduced transconductance and trapped charge within the floating gate structure are minimized, resulting in a lower VT and improved chemical transconductance efficiency. Other characteristics, including chemical sensitivity, reference leakage current, and noise power, are at comparable levels with conventional CMOS-based ISFET devices.