Yuanwen Huang

MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection

Hardware Trojan detection has emerged as a critical challenge to ensure security and trustworthiness of integrated circuits. A vast majority of research efforts in this area has utilized side-channel analysis for Trojan detection. Functional test generation for logic testing is a promising alternative but it may not be helpful if a Trojan cannot be fully activated or the Trojan effect cannot be propagated to the observable outputs. Side-channel analysis, on the other hand, can achieve significantly higher detection coverage for Trojans of all types/sizes, since it does not require activation/propagation of an unknown Trojan. However, they have often limited effectiveness due to poor detection sensitivity under large process variations and small Trojan footprint in side-channel signature. In this paper, we address this critical problem through a novel side-channel-aware test generation approach, based on a concept of Multiple Excitation of Rare Switching (MERS), that can significantly increase Trojan detection sensitivity. The paper makes several important contributions: i) it presents in detail the statistical test generation method, which can generate high-quality testset for creating high relative activity in arbitrary Trojan instances; ii) it analyzes the effectiveness of generated testset in terms of Trojan coverage; and iii) it describes two judicious reordering methods can further tune the testset and greatly improve the side channel sensitivity. Simulation results demonstrate that the tests generated by MERS can significantly increase the Trojans sensitivity, thereby making Trojan detection effective using side-channel analysis.

Trojan localization using symbolic algebra

Growing reliance on reusable hardware Intellectual Property (IP) blocks, severely affects the security and trustworthiness of System-on-Chips (SoCs) since untrusted third-party vendors may deliberately insert malicious components to incorporate undesired functionality. Malicious implants may also work as hidden backdoor and leak protected information. In this paper, we propose an automated approach to identify untrustworthy IPs and localize malicious functional modifications (if any). The technique is based on extracting polynomials from gate-level implementation of the untrustworthy IP and comparing them with specification polynomials. The proposed approach is applicable when the specification is available. Our approach is scalable due to manipulation of polynomials instead of BDD-based analysis used in traditional equivalence checking techniques. Experimental results using Trust-HUB benchmarks demonstrate that our approach improves both localization and test generation efficiency by several orders of magnitude compared to the state-of-the-art Trojan detection techniques.

Trace Buffer Attack: Security versus observability study in post-silicon debug

Since the standardization of AES/Rijndael symmetric-key cipher by NIST in 2001, it gained widespread acceptance in various protocols and withstood intense scrutiny from the theoretical cryptanalysts. From the physical implementation point of view, however, AES remained vulnerable. Practical attacks on AES via fault injection, differential power analysis, scan-chain and cache-access timing have been demonstrated so far. Along this line, in this paper, we propose a novel and effective attack, termed Trace Buffer Attack. Trace buffers are extensively used for post-silicon debug of digital designs. We identify this as a source of information leakage and show that, unless proper countermeasure is taken, Trace Buffer Attack is capable of partially recovering the secret keys of different AES implementations. We report the detailed process of trace-buffer attack with experimental results. We also propose a countermeasure in order to avoid such attack.

Reliability and energy-aware cache reconfiguration for embedded systems

Cache vulnerability due to soft errors is one of the reliability concerns in embedded systems. Dynamic reconfiguration techniques are widely studied for improving cache energy without considering the implications of cache vulnerability. Maintaining a useful data longer in the cache can be beneficial for energy improvement due to reduction in miss rates, however, longer data retention negatively impacts the vulnerability due to soft errors. This paper studies the trade-off between energy efficiency improvement and reduction in cache vulnerability during cache reconfiguration. We propose two heuristic approaches for reliability- and energy-aware dynamic cache reconfiguration. Experimental results demonstrate that our proposed approaches can provide drastic reduction in cache vulnerability with minor impact on energy and performance.

Trace Buffer Attack on the AES Cipher

Since the standardization of AES/Rijndael symmetric-key cipher by NIST in 2001, it gained widespread acceptance in various protocols and withstood intense scrutiny from the theoretical cryptanalysts. From the physical implementation point of view, however, AES remained vulnerable. Practical attacks on AES via fault injection, differential power analysis, scan-chain and cache-access timing have been demonstrated so far. In this paper, we propose a novel and effective attack, termed Trace Buffer Attack. Trace buffers are extensively used for post-silicon debug of integrated circuits. We identify the trace buffer as a source of information leakage. We first report the detailed process of trace buffer attack assuming that the register-transfer level (RTL) implementation is available. We further analyze the AES encryption algorithm and Rijndael’s key expansion algorithm, and illustrate that trace buffer attack is feasible without implementation (RTL) knowledge. Our experimental results show that trace buffer attack is capable of partially recovering the secret keys of different AES implementations.

Test Generation for Detection of Malicious Parametric Variations

Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design/verification cost while meeting aggressive time-to-market constraints. It is crucial to ensure that an IP block is not vulnerable to input conditions that violate its non-functional (parametric) constraints, such as power, temperature, or performance. Power supply voltages, increased integration densities, and higher operating frequencies, among other factors, are producing devices that are more sensitive to power dissipation and reliability problems. Power viruses which have excessive power dissipation can lead to overheating, electromigration, and a reduced chip lifetime. Moreover, large instantaneous power consumption causes voltage drop and ground bounce, resulting in circuit delays and soft errors. As a result, reliability analysis of worst-case peak power and peak temperature has steadily become a critical part of the design process of digital circuits.

SoC Security Versus Post-Silicon Debug Conflict

Design-for-debug structures such as trace buffers are widely used in post-silicon validation to improve the observability. Various design-for-test structures, such as scan chains, are also utilized for observability improvement. While debug engineers would like to have better observability, the security experts would like to enforce limited or no visibility with respect to the security modules. This chapter illustrates that the structures inserted for the benefit of debugging can be a source of information leakage. Specifically, this chapter describes security attacks on both design-for-debug (trace buffer) and design-for-test (scan chain) structures. Experimental results show that trace buffer attack is capable of partially recovering the secret keys of different AES implementations.

Formal Approaches to Hardware Trust Verification

Trust establishment in semiconductor designs has become a major challenge for design houses and government since several countries and companies are involved during different stages of a design life cycle. The variety of vendors increases the risk of security vulnerabilities within the supply chain of integrated circuits. Hardware Trojans are malfunctions which can be inserted during any stage of design such as defining specification, designing intellectual properties (e.g., high-level models, RTL modules, and gate-level netlists), layout extraction, and manufacturing. A triggered hardware Trojan can severely affect the integrity and security of the circuit by causing system failures such as deadlock, denial of service, or granting an unauthorized access to secret information. Hardware Trojans are designed in a way that they are inactive most of the time and can be triggered with a very rare input sequence. Therefore, using simulation-based validation is not effective to detect potential Trojans in a design because of the Trojan’s stealthy nature. In other words, the rare trigger conditions may not be tested during validation time, and a Trojan-inserted circuit cannot be differentiated from a Trojan-free one. From the security perspective, a useful validation approach is the one that can prove the correct functionality of a design, nothing more nothing less. Formal methods are promising to prove the security properties; however, the conventional formal methods suffer from scalability concerns. There are several scalable formal approaches to detect hardware Trojans based on satisfiability solvers, model checkers, theorem provers, symbolic algebra, and combination of them. In this chapter, we discuss hardware trust validation techniques based on formal methods.

Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore Systems

Dynamic cache reconfiguration has been widely explored for energy optimization and performance improvement for single-core systems. Cache partitioning techniques are introduced for the shared cache in multicore systems to alleviate inter-core interference. While these techniques focus only on performance and energy, they ignore vulnerability due to soft errors. In this paper, we present a static profiling based algorithm to enable vulnerability-aware energy-optimization for real-time multicore systems. Our approach can efficiently search the space of cache configurations and partitioning schemes for energy optimization while task deadlines and vulnerability constraints are satisfied. Our experimental results demonstrate that our approach can achieve 19.2% average energy savings compared with the base configuration, while drastically reduce the vulnerability (49.3% on average) compared to state-of-the-art techniques.