Yuanzheng Yue

InAlN/AlN/GaN HEMTs With Regrown Ohmic Contacts and

We report 30-nm-gate-length InAlN/AlN/GaN/SiC high-electron-mobility transistors (HEMTs) with a record current gain cutoff frequency (fT) of 370 GHz. The HEMT without back barrier exhibits an extrinsic transconductance (gm.ext) of 650 mS/mm and an on/off current ratio of 106 owing to the incorporation of dielectric-free passivation and regrown ohmic contacts with a contact resistance of 0.16 Ω·mm. Delay analysis suggests that the high fT is a result of low gate-drain parasitics associated with the rectangular gate. Although it appears possible to reach 500-GHz fT by further reducing the gate length, it is imperative to investigate alternative structures that offer higher mobility/velocity while keeping the best possible electrostatic control in ultrascaled geometry.

f_{T}

We report on 30-nm-gate-length InAlN/AlN/GaN/SiC high-electron-mobility transistors (HEMTs) with a record current gain cutoff frequency (fT) of 400 GHz. Although the high drain-induced barrier lowering (DIBL) value is indicative of significant short-channel effects, more than seven orders of magnitude in the current on/off ratio was observed. The high fT is a result of minimized parasitic effects and at the expense of a low power gain cutoff frequency (fMAX). The gate length dependence and temperature dependence of fT were also measured.

of 370 GHz

A technology similar to silicon-on-insulator is highly desirable for III-V electronics to support scaling for future generations. This letter reports the first realization of strained GaN quantum-well transistors embedded in unstrained AlN as the insulator. The molecular beam epitaxy (MBE)-grown heterostructure consisting of an ultrathin GaN channel buried in strain-free AIN barriers is favorable for scaling by the suppression of short-channel effects. Ohmic contacts are realized with MBE-regrown heavily Si-doped n+ GaN. For long-channel devices, a saturation drain current of ~0.7 A/mm at VGS = +3 V and a peak extrinsic transconductance of ~160 mS/mm around VGS = +1 V are measured at VDS = +10 V. No hysteresis is observed in the C-V measurement, indicating the high quality of all binary nitride heterostructures. The demonstrated device structure offers a high promise for high-frequency and high-power applications in the future. The strain-free barrier has the potential to enhance the reliability of GaN transistors.

Ultrascaled InAlN/GaN High Electron Mobility Transistors with Cutoff Frequency of 400 GHz

Depletion-mode quaternary barrier In_0.13Al_0.83 Ga_0.04N high-electron-mobility transistors (HEMTs) with regrown ohmic contacts and T-gates on a SiC substrate have been fabricated. Devices with 40-nm-long footprints show a maximum output current density of 1.8 A/mm, an extrinsic dc transconductance of 770 mS/mm, and cutoff frequencies <i>fT</i>/<i>f</i>_max of 230/300 GHz at the same bias, which give a record-high value of √<i>fT</i> ·<i>f</i>_max = 263 GHz among all reported InAl(Ga)N barrier HEMTs. The device speed shows good scalability with gate length despite the onset of short-channel effects due to the lack of a back barrier. An effective electron velocity of 1.36 ×10⁷ cm/s, which is comparable with that in the state-of-the-art deeply scaled AlN/GaN HEMTs, has been extracted from the gate-length dependence of <i>fT</i> for gate lengths from 100 to 40 nm.

Ultrathin Body GaN-on-Insulator Quantum Well FETs With Regrown Ohmic Contacts

Depletion-mode high-electron-mobility transistors (HEMTs) with an 11 nm quaternary In0.13Al0.83Ga0.04N barrier and a 5 nm In0.05Ga0.95N channel on SiC substrates have been fabricated. The as-processed HEMT structure features a channel electron density of 2.08×1013 cm-2 and a mobility of 1140 cm2 V-1 s-1. A device with a 50-nm-long T-shaped gate shows a maximum output current density of 2.0 A/mm, a peak extrinsic DC transconductance of 690 mS/mm, and cut-off frequencies fT/fmax of 260/220 GHz at the same bias, representing a record high √fTfmax of 239 GHz for InGaN channel HEMTs.

Quaternary Barrier InAlGaN HEMTs With

The effects of fringing capacitances on the high-frequency performance of T-gate GaN high-electron mobility transistors (HEMTs) are investigated. Delay time components have been analyzed for gate-recessed InAlN/GaN HEMTs with a total gate length of 40 nm and fT/fmax of 225/250 GHz. It is found that the gate extrinsic capacitance contributes significantly to the parasitic delay-approximately 50% of the total delay in these highly scaled devices. The gate extrinsic capacitance comprises two components: 1) parallel plate capacitances between the T-gate and the surrounding electrodes and 2) the fringing capacitance between the gate stem and the access regions. Detailed study of the gate electrostatics reveals that the later, the fringing capacitance between the T-gate stem and the device access region, ultimately determines the lower limit of the extrinsic capacitance Cext; this minimum Cext can be realized experimentally using a large gate stem height and employing low- k passivation dielectric. Since the corresponding parasitic delay can be expressed as Cext/gm,int, this paper also highlights the importance of maximizing gm,int in ultrascaled HEMTs by adopting strategies to enhance carrier velocity.

f_{T}/f_{\max}

The shift of the threshold voltage Vth in Al2O3/InAlN/GaN metal–oxide–semiconductor high-electron-mobility transistors (MOSHEMTs) is demonstrated by CF4 plasma treatments. The accompanying channel mobility degradation is monitored to understand the tradeoff design space. The effective negative charge introduced by the F plasma treatments at the oxide interface is found to be as high as −0.73 × 1013 cm−2 (mobility > 500 cm2 V−1 s−1), sufficient to fully compensate for the net polarization charge in Al0.15GaN/GaN HEMTs. Although it is difficult to obtain Vth 0 V owing to the high polarization charges in InAlN, these MOSHEMTs with 1 µm gates show very low leakage (~1 × 10−11 A/mm), low hysteresis, and low dispersion.

of 230/300 GHz

In this work, signatures of plasma waves in GaN-based high electron mobility transistors were observed by direct electrical measurement at room temperature. Periodic grating-gate device structures were fabricated and characterized by on-wafer G-band (140–220 GHz) s-parameter measurements as a function of gate bias voltage and device geometry. A physics-based equivalent circuit model was used to assist in interpreting the measured s-parameters. The kinetic inductance extracted from the measurement data matches well with theoretical predictions, consistent with direct observation of plasma wave-related effects in GaN-channel devices at room temperature. This observation of electrically significant room-temperature plasma-wave effects in GaN-channel devices may have implications for future millimeter-wave and THz device concepts and designs.

InGaN Channel High-Electron-Mobility Transistors with InAlGaN Barrier and fT/fmax of 260/220 GHz

The origin and management of DC-RF dispersion in InAlN-based GaN high electron mobility transistors (HEMTs) is examined, in conjunction with consideration of the implications for device speed. This study, in which GaN HEMTs with alloyed and non-alloyed ohmic contacts are compared, renders the following observations and hypotheses: 1) We show and explain that dispersion free operation can be achieved without passivation. 2) The root cause of dispersion associated with surface states is often introduced during device processing; in particular, unintentional or un-optimized oxidation of the HEMT surface. 3) These undesired surface states also lead to gate extension (virtual gate), which decreases device speed but increases the breakdown voltage. In addition, the function and efficacy of a plasma-based ultrathin passivation is evaluated.

Effect of Fringing Capacitances on the RF Performance of GaN HEMTs With T-Gates

A wet etch process that produces smooth sidewalls aligned with the m-plane ({ 11¯00}) crystal facets of Ga-polar GaN grown on sapphire is demonstrated by combining photo-electrochemical (PEC) treatment with a postprocessing wet etch step. This novel process results in faceted and extremely smooth vertical etched sidewalls. This two-step process consists of a PEC treatment to define the geometry by converting the region to be removed to an oxide, followed by selective wet-chemical removal of the oxide in buffered HF and post-etch immersion in KOH (0.5 M) at 150 °C to smooth the surface and reveal the crystal planes. The dependence of the PEC treatment parameters (optical intensity, solution composition, direct current bias) on the resulting etch rates and morphology has been investigated.