Yujeong Seo

Transparent Resistive Switching Memory Using ITO/AlN/ITO Capacitors

This letter covers the fabrication of a transparent resistive random access memory (T-ReRAM) device using ITO/AlN/ITO capacitors and its observed resistive switching characteristics. This AIN-based T-ReRAM shows a transmittance above 80% (including the substrate) in the visible region and an excellent switching behavior under ±3 V/10 ns with a high-to-low resistance ratio greater than 102. In the reliability test, the device showed an endurance of >; 108 cycles and a retention time of >; 105 s at 85°C. We believe that the AIN-based T-ReRAM presented in this letter could be a milestone for future see-through electronic devices.

Analysis of electronic memory traps in the oxide-nitride-oxide structure of a polysilicon-oxide-nitride-oxide-semiconductor flash memory

The origin of the electron memory trap in an oxide-nitride-oxide structure deposited on n-type Si is investigated by both capacitance-voltage and deep level transient spectroscopy (DLTS). Two electron traps are observed near 0.27 and 0.54eV, below the conduction band minimum of Si and are identified as the nitride bulk trap and the Si–SiO2 interfacial trap, respectively. The trap depth, viz., vertical distribution of the electron trap, in both nitride bulk and Si–SiO2 interface, are also estimated from the bias voltage dependent DLTS.

Correlation between charge trap distribution and memory characteristics in metal/oxide/nitride/oxide/silicon devices with two different blocking oxides, Al2O3 and SiO2

We examined the origin of the charge traps in bothSiO2/Si3N4/SiO2 (ONO) and Al2O3/Si3N4/SiO2 (ANO) structures and their effect on the memory characteristics by capacitance-voltage (C-V) measurements and deep level transient spectroscopy (DLTS). A larger memory window was observed by C-V for ANO, due to its higher trap density. The DLTS showed that nitride traps are dominant in ANO, while more Si/SiO2 interface-related traps are observed in ONO. The ANO capacitor outperforms the ONO one in terms of both the program efficiency and retention, which is attributed to the reduced number of interface traps in ANO.

Realization of One-Diode-Type Resistive-Switching Memory with Cr-SrTiO3 Film

The authors report a silicon-based one-diode–type resistive-switching memory (RRAM) device with self-rectifying properties and high electrical properties. The RRAM cell consisted of Al/Cr–SrTiO3/Si and revealed intrinsic diode properties, so that unwanted sneaky currents could be removed from an RRAM crossbar array without extra switching devices. The insulator–metal transition property of the proposed device was explained using the space-charge–limited conduction mechanism. The memory device showed good characteristics including high ON/OFF ratio (~106), low reset current (~10-11 A), high speed at low voltage (200 ns, 2 V), and reasonable endurance (>104 cycles) and retention characteristics (>104 s).

A CMOS-Process-Compatible ZnO-Based Charge-Trap Flash Memory

ZnO-based charge-trap Flash technology using a resistive switching mechanism is demonstrated for next-generation nonvolatile memory. This device consists of metal/ZnO/nitride/oxide/silicon in order to make use of the electrical transport in the ZnO resistive switching layer. Compared to the previous devices with perovskite oxide materials used as a conduction path, the proposed device shows faster switching speeds (10 ns/100 μs), lower operation voltages ( ±7 V) for the program/erase ( P/E) states, and higher endurance (106 P/E cycles), along with comparable retention properties.

High-speed and low-voltage performance in a charge-trapping flash memory using a NiO tunnel junction

A novel charge-trapping nonvolatile memory using gate injection switching is demonstrated in this paper. This device is composed of metal/NiO/nitride/oxide/silicon in order to make use of the electrical transport phenomenon found in NiO tunnel junctions. Compared with the reference structure of a conventional metal/oxide/nitride/oxide/silicon memory, the proposed device showed a larger memory window, very fast switching speeds of 100 ns/1 µs and a low operation voltage of ±5 V for the program/erase states. In addition, we observed that a large number of interface states in the bottom oxide were reduced using deep-level transient spectroscopy.

Negative-/Positive-Bias-Instability Analysis of the Memory Characteristics Improved by Hydrogen Postannealing in MANOS Capacitors

We report the effect of hydrogen annealing on the gate-leakage-current and switching characteristics of metal-alumina-nitride-oxide-silicon (MANOS) capacitors by analyzing their negative-/positive-bias instability (NBI/PBI). One sample, namely, A, is annealed with rapid thermal annealing (RTA), and the other sample, namely, B, is first annealed with RTA and then further annealed in a furnace, using a N2-H2 (98% nitrogen and 2% hydrogen) gas mixture. In the NBI/PBI experiments, the flatband voltage shift ΔVFB is observed to be smaller, i.e., the gate-leakage-current density is reduced for sample B at gate voltages less than ±3 V, a domain where trap-assisted tunneling is dominant. However, ΔVFB increases rapidly for the same sample at gate voltages larger than ±6 V, a domain where the modified Fowler-Nordheim tunneling (MFNT) is dominant, which indicates faster program-and-erase characteristics. These results show that additional hydrogen annealing can improve both device reliability and switching characteristics of the MANOS-type memory by reducing interface traps between the silicon substrate and silicon oxide layers, as well as turn-on voltages for MFNT.

Investigation of vertically trapped charge locations in Cr-doped-SrTiO3-based charge trapping memory devices

In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO3/Si3N4 interface to the bulk region of Si3N4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO3/Si3N4 interface by hole injection from the Si substrate into the Si3N4 layer at a high electric field (EOX > 7 MV/cm). In addition, some of these charges passing across the SiO2 (OX) layer generate many Si-SiO2 interface traps (Dit: 1.58 × 1012 cm−2 eV−1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.

Charge trap flash memory using ferroelectric materials as a blocking layer

In this paper, we propose a charge-trap flash memory device using a ferroelectric material, Sr0.7Bi2.3Nb2O9 (SBN), with spontaneous polarization as a blocking layer. This device consists of metal/SBN/nitride/oxide/silicon and has an advantage in the carrier injection into the nitride from the silicon due to polarization charges formed in the ferroelectric material. Compared to conventional metal/oxide/nitride/oxide/silicon memory devices, the proposed devices showed a larger memory window (7 V), faster program/erase (P/E) speeds (100/500 μs), and higher endurance (105 P/E cycles) with comparable retention properties.

Current Versus Voltage Characteristics of a Si Based 1-Diode Type Resistive Memory with Cr-SrTiO 3 Films

In this paper, in order to suppress unwanted current paths originating from adjacent cells in a passive crossbar array based on resistive random access memory (RRAM) without extrinsic switching devices, 1-diode type RRAM which consists of a 0.2% chromium-doped strontium titanate (Cr-) film deposited on a silicon substrate, was proposed for high packing density, and intrinsic rectifying characteristics from the current versus voltage characteristics were successfully demonstrated.