Yuki Niiyama

GaN Power Transistors on Si Substrates for Switching Applications

In this paper, GaN power transistors on Si substrates for power switching application are reported. GaN heterojunction field-effect transistor (HFET) structure on Si is an important configuration in order to realize a low loss and high power devices as well as one of the cost-effective solutions. Current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate. Furthermore, attempts for normally off GaN-FETs were examined. A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance (Ron) and a high breakdown voltage (Vb).

Normally Off n-Channel GaN MOSFETs on Si Substrates Using an SAG Technique and Ion Implantation

We have demonstrated n-channel gallium nitride (GaN) MOSFETs using a selective area growth (SAG) technique and ion implantation on a silicon substrate. Both MOSFETs realized good normally off operations. The MOSFET using the SAG technique showed a large drain current of 112 mA/mm, a lower leakage current, and a high field mobility of 113 cm2/V . s, which is, to our knowledge, the best for a GaN MOSFET on a silicon substrate.

Enhancement-mode gan hybrid mos-hemts with r on,sp of 20 mω-cm 2

We report on the experimental demonstration of a novel n-channel GaN hybrid MOS-HEMT realized on AlGaN/GaN heterostructure on sapphire substrate. This enhancement-mode MOS-gated heterojunction transistor, with 3 mum channel length and 20 mum RESURF length, exhibited a specific on-resistance as low as 20 mOmega-cm2. Simulations indicated the strong dependence of device breakdown voltage on the doping and concentration of the bottom p-GaN layer and its important role in reducing the surface electric field to suppress oxide breakdown.

Over 2 A Operation at 250 °C of GaN Metal-Oxide-Semiconductor Field Effect Transistors on Sapphire Substrates

We investigated normally off operation GaN metal–oxide–semiconductor field effect transistors (MOSFETs). The drain current of GaN MOSFETs with a gate width of 1 mm increased from 0.004 to 0.1 A by which the channel length decreased from 100 to 2 µm. However, the on-resistance was increased by shortening a channel length. In addition, the drain current of GaN MOSFETs with the channel length of 4 µm was increased from 0.08 A to more than 2.2 A, by which the channel width was increased from 1 to 16 mm. As a result, we achieved normally off operation GaN MOSFETs with the highest operation temperature of 250 °C. The drain current was 2.2 A at Vg=+14 V. The threshold voltage (Vth) was +3 V.

Enhancement-mode GaN hybrid MOS-HFETs on Si substrates with Over 70 A operation

We report on the demonstration of enhancement-mode n-channel GaN-based hybrid MOS-HFETs realized on AlGaN/GaN heterostructure on silicon substrates with a large drain current operation. The GaN-based hybrid MOS HFETs realized the threshold voltage of 2.8 V, the maximum drain current of over 70 A with the channel width of 340 mm. This is the best value for an enhancement-mode GaN-based FET. The specific on-state resistance was 16.5 mΩcm2. The breakdown voltage was over 500 V. These results suggest that this structure is a good candidate for power switching applications.

Lateral Implanted RESURF GaN MOSFETs with BV up to 2.5 kV

We report on the demonstration of enhancement- mode n-channel lateral implanted GaN high-voltage MOSFET with breakdown voltage up to 2.5 kV or specific on-resistance as low as 30 mOmegaldrcm2. With proper RESURF dose, drain current up to 0.1 A and breakdown voltage up to 1570 V is realized on the same device. The reliability lifetime defined by the failure criteria of DeltaIp/Ip=20% was determined to be over 11 years at 250degC.

Si Ion Implantation into Mg-Doped GaN for Fabrication of Reduced Surface Field Metal?Oxide?Semiconductor Field-Effect Transistors

We have studied the activation of Si ion implanted un- and Mg-doped gallium nitride (GaN) for the fabrication of reduced surface field (RESURF) metal–oxide–semiconductor field-effect transistors (MOSFETs). By annealing at 1260 °C for 30 s by using rapid thermal annealing (RTA), the activation ratios of un- and Mg-doped GaN with Si doses of 3×1015 cm-2 were ~100 and 73%, respectively. These values are sufficient for application some semiconductor devices. Hardly any diffusion of the Si atoms implanted in GaN was observed by secondary ion mass spectrometry (SIMS). The activation ratio between un- and Mg-doped GaN was markedly different at low doses. The cause of the difference appears to be Mg compensation in GaN. In addition, we fabricated GaN MOSFETs with ion implanted RESURF zones. We also monitored the field-effect transitor (FET) operation and high breakdown voltage of the GaN MOSFETs. The threshold voltage was +2 V. An enhancement mode operation and a breakdown voltage higher 1500 V at a RESURF length of 20 µm were achieved.

Enhancement-mode GaN hybrid MOS-HEMTs with breakdown voltage of 1300V

We have studied and optimized the breakdown voltage of enhancement-mode n-channel GaN hybrid MOS-HEMTs on sapphire substrate. These MOS-gated transistors, with different Mg doped p-type GaN layer underneath the unintentional doped AlGaN/GaN layer, have breakdown voltage as high as 1300V using a dielectric isolation (DI) RESURF approach.

Normally off operation GaN-based MOSFETs for power electronics applications

Gallium nitride (GaN) is a promising electronic semiconductor material for high-power, high-temperature devices due to its remarkable material properties like wide bandgap, large critical electric field and high saturation velocity compared with Si. The metal-oxide–semiconductor (MOS) field-effect transistor (MOSFET) structure can be operated at a positive threshold voltage, namely the normally off mode, which is preferable for power transistors in terms of fail-safe operation. However in order to minimize the power losses in MOSFET operation, good interface quality at SiO2/GaN and low resistance in the n+-contact layer are strongly required. The MOS capacitors were used to characterize the interface states at SiO2/GaN, and the interface state density at Ec − 0.4 eV was less than 1 × 1011 cm−2 eV−1 after annealing at 900 °C for 30 min by the furnace. In addition, the activation annealing of Si-implanted GaN was performed at 1260 °C for 30 s in rapid thermal annealing (RTA) and its sheet resistance was 23 kΩ sq−1. Finally, we have fabricated GaN MOSFETs and have achieved more than 1 A operation in the normally off mode at more than 250 °C. The breakdown voltage was more than 1500 V. We also confirmed more than 100 h of consecutive operation at 250 °C at the moment.

288 V-10 V DC- DC Converter Application Using AlGaN/GaN HFETs

We report on the 288 V-10 V DC- DC converter circuit using AlGaN/GaN HFETs for the first time. The AlGaN/GaN HFET with a large current and a high breakdown voltage operation was fabricated. That is, the maximum drain current was over 50 A, and the minimum on-resistance was 70 mohm. The breakdown voltage was over 600 V. A DC-DC down-converter from input DC 288 V to output DC 10 V was fabricated using these HFETs. It was confirmed that the switching speed of the AlGaN/GaN HFET was faster than that of Si MOSFET. The DC-DC down-converter was fabricated using these HFETs. This converter was composed of a full bridge circuit using four n-channel AlGaN/GaN HFETs. In the case of AlGaN/GaN HFET, a gate switching wave (Vgs) and source-drain wave (Vds) were abrupt compared with those of using Si MOSFETs. In both cases, a stable and constant output DC 10V was also obtained and the conversion efficiency of the converters with AlGaN/GaN HFETs was 84%.