T.P. Chow

Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics

The impact of interconnection parasitic inductance on MOSFET switching characteristics is modeled analytically and evaluated experimentally. Closed-form analytical equations are derived to evaluate switching characteristics due to common source inductance and switching loop inductance. Assuming an identical total parasitic inductance, a MOSFET with higher common source inductance has higher switching energy loss but lower overshoot voltage than a MOSFET with higher switching loop inductance. The tradeoffs between switching loss and signal overshoot and oscillation are included in design criteria for optimizing switching performance of packaged power electronics. The experimental results are in good agreement with the analytical modeling.

1300-V 6H-SiC lateral MOSFETs with two RESURF zones

A two-zone, lateral RESURF field 6H-SiC MOSFET with breakdown voltage as high as 1300 V and specific on-resistance of 160 m/spl Omega//spl middot/cm/sup 2/ has been fabricated. These MOSFETs exhibit stable and reversible breakdown indicating avalanche breakdown in SiC that has not been reported in earlier lateral SiC MOSFETs.

High-voltage lateral RESURF MOSFETs on 4H-SiC

Owing to high critical electrical breakdown field and large energy gap, SiC has been established as the most promising candidate for high-voltage power semiconductor devices. In the past few years, several high-voltage vertical MOS devices have been demonstrated in SiC, whereas only a 2.6 KV lateral SiC MOSFET has been reported so far. Lateral integrable REduced SURface Field (RESURF) devices are key building blocks for high-voltage power ICs. In this work, we present the first experimental demonstration of a n-channel lateral RESURF MOSFET fabricated on 4H-SiC. The devices exhibit a blocking voltage in excess of 1200 V with a best specific on-resistance of 4 ohm-cm/sup 2/.

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 /spl Omega/-cm/sup 2/. The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability.

930-V 170-m/spl Omega//spl middot/cm/sup 2/ lateral two-zone RESURF MOSFETs in 4H-SiC with NO annealing

The first lateral two-zone reduced surface field MOSFETs in 4H-SiC with NO annealing are reported. Interface properties of 4H-SiC-SiO/sub 2/ are improved, with inversion layer field-effect mobility increased to 25 cm/sup 2//V/spl middot/s, five times higher than that of dry reoxidation process, and with channel resistance significantly reduced. Devices are normally off with low leakage current. Threshold voltage is around 3 V. Blocking voltage of 930 V and specific on-resistance of 170 m/spl Omega//spl middot/cm/sup 2/ were obtained. Large-area devices with multifinger geometry are also demonstrated with scaled-up current. The output characteristics exhibit excellent linear and saturation regions.

Experimental Demonstration of Novel High-Voltage Epilayer RESURF GaN MOSFET

We report on the experimental demonstration of a novel n-channel GaN epilayer RESURF GaN MOSFET with good tradeoff between breakdown voltage and specific on-resistance for the first time. Device with 4-mum channel length and 16-mum RESURF length has breakdown voltage up to 730 V with specific on-resistance 34 mOmegamiddotcm2 (VG - VT = 20 V), best reported to date.

Accumulation-layer electron mobility in n-channel 4H-SiC MOSFETs

Accumulation-layer electron mobility in n-channel depletion-mode metal oxide semiconductor field effect transistors (MOSFETs) fabricated in 4H-SiC was investigated using Hall-measurements. The accumulation-layer mobility showed a smooth transition from the bulk value (/spl sim/350 cm/sup 2//V-s) in the depletion regime into accumulation (/spl sim/200 cm/sup 2//V-s). In contrast, the field-effect mobility, extracted from the transconductance, was found to be much lower (/spl sim/27 cm/sup 2//V-s), due to the trapping of the field-induced carriers by interface states. Though the current in depletion/accumulation-mode MOSFETs can be high due to the contribution of bulk conduction resulting in low on-resistance, carrier trapping will cause the transconductance to be low in the accumulation regime.

Characteristics of 4H-SiC P-i-N diodes on lightly doped free-standing substrates

This paper presents static and dynamic electrical characteristics of implanted 4H-SiC PiN diodes fabricated on Si-face and C-face of lightly doped free-standing substrates. The device performance is found to be comparable to conventional diodes. Carrier lifetime of about 2.5 μs was measured for the drift region.

Physics-based analytical model for high-voltage bidirectional GaN transistors using lateral GaN power HEMT

A bidirectional switching GaN transistor, PCB-packaged using commercially available high voltage power GaN HEMTs (200V, 3A) from EPC, has been modeled and characterized. A physics-based FET model, originally developed by Statz for short-channel GaAs MESFET, has been adapted to model both static and switching characteristics of both the constituent HEMT and the bidirectional switch up to 125°C. We have found that the Statz model is superior to conventional short-channel MOSFET models due to the mixed pentode-triode on-state I-V characteristics of the EPC GaN HEMT. The bidirectional GaN transistor exhibits linear operation as well as bidirectional current saturation, offering low on-state resistance along with current limiting capabilities.

Hysteresis in transfer characteristics in 4H-SiC depletion/accumulation-mode MOSFETs

Hysteresis in room-temperature transfer characteristics between forward (pinch-off voltage, V/sub P/=-15 V) and reverse gate voltage sweeps (V/sub P/=7 V) in n-channel depletion/accumulation-mode 4H-SiC MOSFETs is reported. Transfer characteristics exhibit a parallel shift toward negative voltages depending,on the starting gate voltage and direction of the sweep. The hysteresis and shift in transfer characteristics are related to changes in effective fixed-oxide charge resulting from changes in interface trap occupancy. Interface trap occupancy changes depending on the magnitude of the starting gate voltage and the direction of gate-voltage sweep. At high temperatures, the hysteresis between forward and reverse gate voltage sweep decreases.