Yuling Niu
Binghamton University
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Featured researches published by Yuling Niu.
electronic components and technology conference | 2015
Yuling Niu; Hohyung Lee; Seungbae Park
During microelectronic manufacturing, a wafer undergoes many fabrication processes. Such processes include exposing a wafer to high temperature. Significant residual stresses are built up in a wafer and they are manifested as warpage of a wafer. Understanding the wafer behavior, especially warpage, during reflow process becomes one of the most important things in developing assembly process. Three Dimensional (3-D) digital image correlation (DIC), as a non-contact optical deformation measurement method, documents both in-plane and out-of plane deformation. The in-situ measurement capability allows to understand a wafer (or a wafer with multiple chips) behavior during reflow (or assembly) process. However, an object such as a monotonic surface or a mirror like wafer needs artificial speckles on the sample surface to be discernable and measured by DIC technique. To avoid contamination on wafer for surface treatment, a speckle-free 3D DIC method is proposed and its effectiveness is investigated. This method introduces an optical pattern projection method and subsequent processes in documenting topography of a wafer placed in an environmental chamber to mimic a reflow process. To validate the new method, warpage measurement result is compared with the measurement from optical profiler, a white light interferometer, and its accuracy and sensitivity are assessed quantitatively.
Volume 1: Advanced Packaging; Emerging Technologies; Modeling and Simulation; Multi-Physics Based Reliability; MEMS and NEMS; Materials and Processes | 2013
Liang Xue; Yuling Niu; Hohyung Lee; Da Yu; Satish C. Chaparala; Seungbae Park
The needs of glass to resist the scratches, drops impact, and bump from everyday use lead to the importance of investigation of the glass fracture under dynamic impact loading. The strength of the glass under dynamic fracture conditions is significantly larger than that under quasi-static loading. There are several theoretic models. In this study, an accumulated damage model is implemented. The relation among the stress, loading rate, contact time and the fracture is investigated. The effect of impact area, impact energy and impact momentum on the glass fracture has been proved to further improve the dynamic fracture criterion of glass. For the experimental studies, the Digital Image Correlation (DIC) method enables one to obtain the first principal strain of the glass during the impact process. Moreover, the FEA model is developed in ANSYS/LS-DYNA™.
Sensors | 2017
Shuai Shao; Dapeng Liu; Yuling Niu; Kathy O’Donnell; Dipak Sengupta; Seungbae Park
Reliability risks for two different types of through-silicon-vias (TSVs) are discussed in this paper. The first is a partially-filled copper TSV, if which the copper layer covers the side walls and bottom. A polymer is used to fill the rest of the cavity. Stresses in risk sites are studied and ranked for this TSV structure by FEA modeling. Parametric studies for material properties (modulus and thermal expansion) of TSV polymer are performed. The second type is a high aspect ratio TSV filled by polycrystalline silicon (poly Si). Potential risks of the voids in the poly Si due to filling defects are studied. Fracture mechanics methods are utilized to evaluate the risk for two different assembly conditions: package assembled to printed circuit board (PCB) and package assembled to flexible substrate. The effect of board/substrate/die thickness and the size and location of the void are discussed.
intersociety conference on thermal and thermomechanical phenomena in electronic systems | 2016
Shuai Shao; Dapeng Liu; Yuling Niu; Seungbae Park
Wafer dicing is a necessary and important process in the microelectronics fabrication. Emerging technologies of IC semiconductor have been utilizing silicon-on-insulation (SOI) wafers. These wafers have made wafer dicing quite challenging. Compared to conventional blade dicing, stealth dicing has advantages such as debris-free and dry process. MEMS dies that are fabricated on a SOI wafer and then undergo stealth dicing is studied in this paper. Cracks were found around the edges of the membrane in the MEMS dies after stealth dicing. The failure causes are to be determined. Three processes in the stealth dicing are studied: IR laser scanning, tape dicing and peeling process. Effects of these three processes on the die stresses were investigated. It is the first time that die stresses in a membrane-structured MEMS on SOI wafer in stealth dicing are analyzed. Thermal/structural stress contours are obtained by finite element analysis. Die stresses caused by these three processes are compared.
ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2017 Conference on Information Storage and Processing Systems | 2017
Jing Wang; Yuling Niu; Seungbae Park
In this study, the moisture induced delamination behavior of a plastic ball grid array package under the solder reflow process was investigated by the finite element analysis. The entire moisture history of the PBGA package was simulated for preconditioning at moisture sensitivity level 1 and the subsequent exposure to a soldering reflow. A fracture mechanics based analysis was used to investigate the combined effects of temperature, moisture and vapor pressure on the delamination behavior at the die/molding compound and die/die attach interfaces during solder reflow. For determining the total strain energy release rate and total stress intensity factor under a multiphysics environment like reflow, researchers commonly used the principle of superposition to combine the results from individual thermal stress, hygroscopic stress and vapor pressure induced stress analyses. In this study, a new method was proposed to obtain the total strain energy release rate and total stress intensity factor under the multi-physics environment in a single fracture analysis instead of three. Two different methods-virtual crack closure technique (VCCT) and crack tip opening displacement method (CTOD) were employed and compared in studying the variation of strain energy release rates during lead-free solder reflow. The relationship between the strain energy release rate and crack length was also obtained. The developments of the stress intensity factors due to individual effect of thermal mismatch, hygroscopic swelling and vapor pressure were calculated. The mode mixity was also determined under different temperatures and crack length.Copyright
electronic components and technology conference | 2016
Yuling Niu; Huayan Wang; Shuai Shao; Seungbae Park
electronic components and technology conference | 2018
Jing Wang; Yuling Niu; Seungbae Park; Alexander Yatskov
electronic components and technology conference | 2018
Van-Lai Pham; Yuling Niu; Jing Wang; Huayang Wang; Charandeep Singh; Seungbae Park; Cheng Zhong; Sau Wee Koh; Jifan Wang; Shuai Shao
electronic components and technology conference | 2018
Shuai Shao; Yuling Niu; Jing Wang; Ruiyang Liu; Seungbae Park; Hohyung Lee; Gamal Refai-Ahmed; Laurene Yip
electronic components and technology conference | 2018
Jiefeng Xu; Yuling Niu; Stephen R. Cain; Scott McCann; Ho Hyung Lee; Gamal Refai-Ahmed; Seungbae Park