Yumei Zhou

A varying pulse width 5 th -derivative gaussian pulse generator for UWB transceivers in CMOS

A fully integrated, ultra low-power, varying pulse width fifth-order derivative Gaussian pulse generator designed and fabricated in a commercial 0.18 mum CMOS technology is reported for 3-10 GHz impulse ultra wideband (UWB) transceivers. The fifth-order derivative Gaussian pulse generator circuit consists of four parallel Gaussian pulse formation blocks and an output stage. It can generate UWB pulse signals with adjustable pulse width ranging from 240 picoseconds to a few nanoseconds. Measurement results show very short UWB pulses with amplitude of 51 mV and an ultra low power consumption of 3.6 mW at 100 MHz pulse repeating frequency (PRF) with 1.8 V power supply voltage. This pulse generator fully complies with FCC UWB power mask.

1.8 pJ/Pulse Programmable Gaussian Pulse Generator for Full-Band Noncarrier Impulse-UWB Transceivers in 90-nm CMOS

This paper presents a single-chip ultralow power programmable Gaussian pulse generator (PG) designed and implemented in the 90-nm CMOS for 3.1-10.6 GHz full-band impulse-radio ultrawideband (UWB) transmitters. Measurement shows that this novel simple two-inverter-based PG achieves the lowest reported power dissipation of merely 1.8 pJ/pulse with a 100-MHz pulse-repeating frequency at 1-V supply, extremely short and programmable pulsewidth ranging from 150 to 350 ps while covering the full 3.1-10.6 GHz UWB spectrum, and a very small area of 0.0068 mm2. It supports up to 6 Gb/s data rate for UWB wireless streaming. A new Federal-CommunicationCommission-aware Gaussian PG design optimization method is discussed and verified experimentally.

FCC-EIRP-aware UWB pulse generator design approach (invited)

This paper reviews a systematic method for design and analysis of high-order Gaussian pulse generators (PG) for carrier-free impulse-radio ultra wideband (IR-UWB) transceivers, which enables to achieve PG performance optimization and FCC effective isotropic radiated power (EIRP) compliance simultaneously. The new FCC-EIRP-aware design method is verified experimentally using Gaussian PG circuits with different derivative orders designed in CMOS.

A Broadband CMOS Multiplier-Based Correlator for IR-UWB Transceiver SoC

A multiplier-based correlator is an important component for impulse radio ultra-wideband (IR-UWB) receiver. Classified as correlation-type demodulator, this type of correlator uses correlation-type demodulation. This paper reports design and implementation of a fully integrated low-power broadband multiplier-based correlator for a 3.1-10.6 GHz full-band UWB receiver in 0.18 mum CMOS that consists of an UWB multiplier and a first-order RC integrator with a 200 MHz bandwidth Measurement results confirm the correlation-type demodulation function and achieve a conversion gain of 0 dB, noise figure of 8.2 dB and power consumption 52 mW for the UWB multiplier.

A 52-mW 3.1–10.6-GHz Fully Integrated Correlator for IR-UWB Transceivers in 0.18

Correlators play key roles in impulse radio ultrawideband (IR-UWB) transceivers. Multiplier-based correlator performs correlation-type demodulation in addition to select desired UWB signals by correlating incoming pulses with templates. This paper reports design and implementation of a fully integrated low-power broadband multiplier-based correlator for a 3.1-10.6-GHz fullband IR-UWB receiver in 0.18 μm CMOS that consists of a UWB multiplier core, two UWB pulse generators, single-ended-to-differential-ended converter, a first-order RC integrator with a 200-MHz bandwidth, and a buffer. Measurement results confirm desired correlation-type demodulation and correlation functions with a conversion gain of 11.03 dB, noise figure of 15.7 dB, very low power consumption of 52 mW and a 1-dB compression point of better than -0.8 dBm over a 7.5-GHz bandwidth.

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A fully integrated, ultra low-power, varying pulse width second-order derivative Gaussian pulse generator designed and fabricated in a commercial 0.18mum CMOS technology is reported for 3-10GHz ultra wideband (UWB) transceivers. The second-order derivative Gaussian pulse generator circuit consists of three cascaded stages for generating square wave, Gaussian impulse, and second-order derivation sequentially. This CMOS second-order derivative Gaussian pulse generator can generate UWB pulses with adjustable pulse width ranging from 220 picoseconds to a few nanoseconds. Measured circuit performance achieves a very short pulse width of <1ns, an amplitude of 70mV and an ultra low power consumption of 2mW at 100MHz pulse repeating frequency. The pulse generator fully complies with FCC power mask.

CMOS

Presented is a novel source-follower-based (SFB) bi-quad cell suitable for realizing continuous-time zero-pole type filters. Unlike the conventional SFB bi-quad cells that can only realize complex poles, additional complex zeros can be synthesized in the proposed one, by adding two feedforward capacitors. A 4th-order Chebyshev II fully differential low-pass filter prototype was fabricated in a 0.18-µm CMOS process. The achieved bandwidth is 2.75 MHz with +5 dBm in-band IIP3 and −1 dB gain. The power consumption is 3 mV at a 2-V supply.

A Varying Pulse Width Second Order Derivative Gaussian Pulse Generator for UWB Transceivers in CMOS

RF ESD protection circuitry design emerges as a big challenge to RF IC design, where the main problem is associated with performance degradation of RF IC due to ESD-induced parasitics. It has been difficult to incorporate the ESD impacts into RF IC design due to lack of proper co-design approach and ESD device models. This paper presents a new ESD-RFIC co-design methodology, including RF ESD design optimization and characterization, as well as RF I/O re-matching techniques, developed to enable wholechip design optimization of ESD-protected RF IC circuits, which is verified by practical designs in 0.18 mum RFCMOS.

Source-follower-based bi-quad cell for continuous-time zero-pole type filters

A new ESD-sensitive LNA design method is presented, featuring S-parameter modelling and input matching network re-matching techniques for ESD+LNA full-chip design optimization. Design of 5 GHz LNA with 5 kV ESD protection in a 0.18 mum RFCMOS technology shows ESD-induced performance reduction in gain and noise figure up to -14.3% and +18% over a 1.8 GHz bandwidth range, which can be recovered by +76.3% and 63%, respectively, by using the proposed design technique.

(Invited) ESD-RFIC Co-design methodology

This paper reports system design and simulation of a new 7.5 GHz single-band carrier-free impulse ultra wideband (I-UWB) system. I-UWB system is developed for high payload wireless video/multimedia streaming applications. To achieve high throughput (>100 Mbps) and high simplicity, I-UWB system adopts a single-full-band (3.1 GHz to 10.6 GHz), pulse-based non-carrier architecture. The system features BPSK modulation and 5th order derivative Gaussian pulsing. Synchronization is assumed between the transmitter and the receiver. The I-UWB system is designed using MATLAB SIMULINK, which achieves a high data rate of 200 Mbps in AWGN channel with good bit error rate (BER) at a signal to noise ratio (SNR) of -12 dB.