Yung-Kwon Sung

Hot-carrier-induced circuit degradation in actual DRAM

The hot-carrier effects on DRAM have been evaluated thoroughly by investigating the performance degradation of each constituent circuit as component transistor aging in a 64 Mb DRAM. The mechanism of how the overall circuit performance is affected by unit transistor aging and which transistors cause most critical circuit performance failures is discussed. It was found that hot-carrier-induced transistor aging in the circuit block did not directly affect the speed degradation, but instead, seriously reduced the design margin of the analog circuit. The circuit performance degradation caused by hot-carrier stress depended more on the circuit structure including output loading rather than the voltage level. In addition, on-chip hot-carrier stress/test patterns were also used to investigate the influence of different output loads of inverter on the dynamic hot-carrier degradation. It was found that the inverter with heavy output load showed less degradation in comparison to the inverter with small load.

Analysis of circuit degradation due to hot-carrier effects in 64Mb DRAMs

Abstract In this paper we detail the consequences of hot-carrier effects on the performance of a 64 Mb DRAM, by investigating the performance degradation of each constituent circuit on the overall performance of the part. This contrasts to the more traditional approach of measuring component transistor aging and applying an arbitrarily derived acceptable drift limit. The mechanism of overall circuit aging, how it relates to the degradation of individual transistor aging and which transistors are most critical to overall DRAM performance is discussed. It was found that hot-carrier-induced transistor aging of the circuit block does not directly affect speed degradation; however, it does seriously reduce the design margin of the analog circuit components of a DRAM. The circuit performance degradation caused by hot-carrier stress depends more on the circuit structure including the output loading conditions than on the absolute voltage level. On-chip hot-carrier stress/test patterns were also used to investigate the influence of output loads of inverter on dynamic hot-carrier degradation. It was found that the transistor in inverter driving a heavy output load showed less degradation than a comparable transistor in inverter driving a smaller load.

Hot-carrier-induced gate capacitance variation and its impact on DRAM circuit functionality

In this paper we detail the consequences of hot-carrier effects on gate capacitance variation and its impact on the design margin of each constituent circuit of a 64 Mb DRAM. The degradation mechanism, which produces the capacitance imbalance in specific circuit blocks, is the combination of the increase of gate capacitance in PMOSFET, and the decrease of gate capacitance in NMOSFET. The two dimensional device simulation using MEDICI was also carried out to investigate the gate capacitance variation as a function of total trapped charge density and its physical length in channel region.

The passivation of GaAs by laser CVD

In this study, properties of GaAs passivation films formed by laser CVD method are investigated. In order to develop GaAs devices, it is necessary to form insulators with good chemical stability, dielectric and interface properties on the GaAs surface in view of application to surface passivation and devices fabrication. SiN films were photolytically deposited by excimer laser with 193 nm wave length on P type [100] GaAs wafer in SiH/sub 4/, NH/sub 3/ and N/sub 2/ gas mixture by varying the substrate temperature from 100/spl deg/C to 300/spl deg/C. The thickness and refractive index of the films as a function of substrate temperature were measured by a nanoscope and ellipsometer respectively. The chemical depth profiles of SiN films were obtained using Auger depth spectroscopy. In order to investigate interface properties of the SiN-P GaAs, MIS structure is made by Al electrode evaporation on SiN films and high frequency C-V and DLTS (Deep Level Transient Spectroscopy) measurements were carried out. And also, surface leakage current was measured between two Au/Ge evaporated electrodes separated 10 /spl mu/m apart on P type GaAs wafer before and after SiN film formation. As the result, deposition rate of SiN films increases as substrate temperature increases, which is due to generation of more reactive species with increasing substrate temperature. Auger depth profiles indicate that diffusion length of Ga and As atoms toward SiN films is reduced as substrate temperature decreases. From the high frequency C-V curve, the hysteresis effect is reduced as substrate temperature decreases and interface trap density obtained from DLTS signals is lowered to 10/sup 12/-10/sup 13/ in the substrate temperature ranging from 100/spl deg/C to 200/spl deg/C. In addition the passivated SiN film on GaAs by laser CVD shows less surface leakage current compared with non-passivated GaAs.<<ETX>>

A study of hot-carrier-induced mismatch drift: a reliability issue for VLSI circuits

The mismatch drift of dynamic circuits, which must be corrected by precharging before activation, is a fundamental process and device reliability issue for very large scale integration (VLSI) circuits. In this paper, we report the consequences of hot-carrier effects on gate capacitance variation and its impact on the mismatch drift of MOS dynamic circuits. It is shown here that the impact of hot-carrier-induced gate capacitance variation on VLSI circuits is more critical than DC parameter (saturation current, threshold voltage, etc.) degradation. An electron beam probing was performed on a 64 Mb DRAM chip to detect the influence of gate capacitance variation in dynamic circuit blocks before and after hot-carrier stress.

Analysis of mechanisms for hot-carrier-induced VLSI circuit degradation

In this paper we discuss in detail the mechanism for hot-carrier induced circuit degradation in actual 64Mb DRAM (dynamic random access memory), by investigating the DRAM specification parameter shift due to transistor aging in each of the constituent circuits. It was found that hot-carrier induced transistor aging of the circuit block does not directly affect the internal clock speed degradation, however, it does greatly reduces the design margin of a circuit which suffers from heavy loads. In addition, an in-depth study of the dynamic hot-carrier degradation behavior of N-channel transistors more common in actual VLSI circuits was carried out based on the alternating stress and charge pumping techniques.

A Study of Deposition Mechanism of Laser CVD SiO 2 Film

This study was performed to investigate the deposition mechanism of SiO by ArF excimer laser(l93nm) CVD with SiH6/ and NO gas mixture and evaluate laser CVD quantitatively by modeling. With ArF excimer laser CVD, thin films can be deposited at low temperature(below 300), with less damage and good uniformity owing to generation of conformal reaction species by singular wavelength of the laser beam. In this study, new model of SiO deposition process by laser CVD was introduced and deposition rate was simulated by computer with the basis on this modeling. And simulation results were compared with experimental results measured at various conditions such as reaction gas ratio, chamber pressure, substrate temperature and laser beam intensity.

The Passivation of GaAs Surface by Laser CVD

In order to passivate the GaAs surface, silicon-nitride films were fabricated by using laser CVD method. SiH and NH were used to obtain SiN films in the range of 100∼300 on p-type (100) GaAs substrate. To determine interface characteristics of the metal-insulator-GaAs structure, electrical measurements were performed such as C-V curves and deep level transient spectroscopy (DLTS). The results show that the hysteresis was reduced and interface trap density was lowered to 1,012 ∼ 1,013 at 100 ∼ 200. According to the study of surface leakage current, the passivated CaAs has less leakage current compared to non-passivated substrate.

Latchup characterization of high energy ion implanted new CMOS twin wells that comprised the BILLI (buried implanted layer for lateral isolation) and BL/CL (buried layer/connecting layer) structures

We have investigated the latchup characteristics of various CMOS well structures possible with high energy ion implantation processes, including conventional retrograde well, BILLI well and BL/CL structure. We also compare those characteristics with conventional diffused wells in bulk and retrograde wells with STI isolation technology. We show DC latchup characterization results that allow us to evaluate each technology and suggest guidelines for the optimization of latchup hardness.

Properties of Pt/Cr layers due to fabrication conditions and micro hot-plate thermal characteristics [gas sensors]

We studied the electrical and structural properties of Pt/Cr layers to fabricate the micro hot-plate for the first time. Increasing the Cr layer thickness, the sheet resistance decreased greatly. The Pt/Cr layer sheet resistance is not affected by the Cr layer thickness. When we annealed the Pt/Cr layer in Ar ambient varying the temperature from 500/spl deg/C to 700/spl deg/C, the sheet resistance varied from 2.026 /spl Omega///spl square/ to 0.6317 /spl Omega///spl square/. We analyzed the Pt/Cr layer properties according to the annealing conditions by XRD and AES depth profiles. We fabricated the micro hot-plate using the Pt/Cr layer by micromachining technology and measured the thermal characteristics by an IR thermo-vision system. The micro-hot plate was simulated by FIDAP and its results compared for the first time.