Yoonjong Huh

Chip-level charged-device modeling and simulation in CMOS integrated circuits

Electrostatic discharge (ESD) accounts for over 30% of chip failure which occurred during chip manufacturing. Inadvertent touching by human body or contact with assembler tray can lead to such ESD failures. The most dominant ESD model is the charged-device model (CDM) wherein energy-destructive failure is incorporated resulting from rapid inflow, or outflow, of high current. Conventional modeling and simulations of the CDM are engineered to describe the behavior of ESD protection circuits, hence have a limitation to account for chip-level charge transfer. This paper presents a new methodology to simulate CDM behavior at chip level. A hierarchical approach associated with a CDM macromodel is developed to model a full-chip structure comprised of several functional subsystems and multiple power supplies. Full-chip CDM simulation provides the analysis of chip-level discharge paths and failure mechanisms, especially focusing on the gate oxide reliability. The proposed method can easily be applied to the CDM failure analysis of any product ICs in the early design stage. As an example, simulation results of a mixed-signal application-specific integrated circuit processed in a 0.25-/spl mu/m CMOS technology show high correlation with the measurement data.

Chip-level simulation for CDM failures in multi-power ICs

This paper presents a new chip-level simulation methodology for charged-device model (CDM) failure analysis in multi-power ICs. A circuit model considering reported CDM failures and efficient simulation is proposed and incorporated with the circuit-level ESD simulator, iETSIM. The CDM behaviors in multi-power ICs are analyzed and the vulnerable sites to CDM stress can be predicted by chip-level simulation. Simulation results are verified by CDM testing of a 0.25 /spl mu/m CMOS ASIC and show good correlation. This simulation methodology at the full-chip level enables us to address CDM failure issues before the detailed chip floorplan and power grid networking are started.

ESD design rule checker

Electrostatic discharge (ESD) protection circuitry is essential for every I/O cell design and has its own set of design rules. These design rules are not only complex but also beyond the scope of commercial DRC tools. In this paper, we present the framework of our ESD design rule checker, and address some of the open issues in the ESD design rule checker presented by Sinha et al. (1998).

A study of ESD-induced latent damage in CMOS integrated circuits

ESD-induced latent damage in CMOS integrated circuits has been thoroughly investigated after cumulative low-level ESD stress. A study of the latent damage for transistors at the package level has been performed with various kinds of ESD stress modes. The impact of latent damage on circuit performance degradation was also evaluated using a 64 Mb DRAM chip as a DUT.

Full chip ESD design rule checking

Electrostatic discharge (ESD) protection is essential for reliability and high yield. ESD design rule checking, however, is beyond the scope of commercial DRC tools. We have presented previously an ESD design rule checker for individual I/O cells. Full chip ESD design rules come in a myriad number of ways and are heavily process dependent. To check them one by one requires rewriting the design rule checker program for each process generation. This paper presents a framework for full chip ESD design rule checking adaptive to how full chip ESD design rules are derived.

Design of ESD power protection with diode structures for mixed-power supply systems

The coupling noise immune electrostatic discharge (ESD) protection network is becoming a critical design requirement for preserving the performance of high-speed analog circuits. In this paper, we present a noise-aware design of ESD power protection with diode structures in highly integrated high-speed CMOS ICs. We thoroughly characterize the noise coupled from the ESD power protection network and experimentally verify its generation and impact on the performance of analog circuitry being protected. A noise-aware design technique is proposed to achieve superior noise isolation while improving ESD reliability. The estimation of peak overvoltage on power/ground busses in digital circuits adaptively finds the optimum feature of protection circuits subject to noise constraints. The design is validated with measurements from a test chip fabricated in a 0.18-/spl mu/m CMOS technology.

Automated extraction of parasitic BJTs for CMOS I/O circuits under ESD stress

The layout of chip I/O heavily relies on design expertise and guidelines due to the lack of supporting CAD tools. Visual inspection of layout by experts to pinpoint design or layout flaws is common industrial practice for I/O verification. In order to meet industrial demand for I/O verification tools, we have developed a layout extractor which targets the reliability issues of CMOS chip I/Os, with specific emphasis on electrostatic discharge (ESD). In this paper, we present an automated systematic approach for identification of parasitic bipolar junction transistors (BJTs) under ESD stress. The extracted circuit netlist can be simulated by an ESD circuit-level simulator.

Understanding and addressing the noise induced by electrostatic discharge in multiple power supply systems

The design of on-chip ESD protection has become increasingly difficult and critical because of shrinking device feature sizes, high operating speed, and system on a chip (SoC) environments. A complex ESD protection network in an SoC can cause the degradation of circuit performance during normal operation. The loss introduced by ESD stress and protection networks is defined as ESD noise. In this paper, we present the generation and characterization of three different types of noise induced by ESD. The effect of ESD protection networks on sensitive circuits is investigated with a test chip processed in a 0.18 /spl mu/m CMOS technology. Experimental results suggest appropriate optimization of a tradeoff between ESD robustness and power supply coupling. It is important to note that, for mixed-signal design, the performance of a sensitive circuit is highly dependent on the ESD noise generated in the vicinity of the sensitive circuit, as well as circuit design techniques.

Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology

This paper reports the effect of electrostatic discharge (ESD) induced impedance mismatch on the performance degradation in high speed I/O interfaces. The impedance mismatch after ESD stressing is explained by on-chip termination resistance distortion. From the circuit-level ESD simulation and experimental results. ESD induced termination resistance degradation should be taken into consideration in the design of the high speed I/O circuits. Proposed design optimization methods of on-chip termination resistors provide sufficient safeguard against ESD damage and improve I/O signal integrity.

Noise-aware design for ESD reliability in mixed-signal integrated circuits

The design of electrostatic discharge (ESD) protection network in CMOS technology becomes increasingly more difficult because of shrinking device feature sizes, high operating speed, and system on a chip (SoC) environment. For SoC protection, many additional considerations are required such as complex power bus architecture, area overhead by protection circuits, and noise isolation during normal operations. We present a novel noise-aware design technique for superior noise margin and improved ESD reliability. The use of hierarchical electrostatic discharge (HED) provides a low impedance discharge path for any ESD event with smaller protection circuitry. The estimation of maximum power/ground voltage in digital circuits is helpful to determine an optimal topology of power clamp circuits subject to noise constraints. Experimental results demonstrate the effectiveness of this method.