Yung-Lin Huang
National Taiwan University
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Publication
Featured researches published by Yung-Lin Huang.
international symposium on vlsi design, automation and test | 2015
Chun-Pang Wu; W.-C. Kuo; H.-J. Wang; Yung-Lin Huang; Yu-Hao Chen; Yi-Hong Chou; Shih-An Yu; Shey-Shi Lu
A batteryless wearable ECG monitoring system-in-a-patch assembled by a biocompatible and pliable silicon-in-parylene technology is introduced. The system is capable of processing the acquired ECG signal and detecting arrhythmia by a built-in digital signal processor (DSP). An NFC communication system is used to interface the external reader. The silicon also integrates a sub-threshold ultra-low-voltage (ULV) boost converter to harvest body heat energy from a thermoelectric generator (TEG) attached to the chest to power up the ECG system. The boost converter operates with no external kick-off circuitry, and the average efficiency is up to 60%. The assembled all-in-one system achieves a very low profile (<;0.9mm); it includes one CMOS die, two SMD inductors (for the boost converter), and two in-parylene gold coils (for the NFC communication system). The pliable parylene mold provides excellent adhesion and skin comfort.
international conference on consumer electronics berlin | 2013
Ku-Chu Wei; Yung-Lin Huang; Shao-Yi Chien
Free-viewpoint TV provides an interactive selection of viewpoints when people watch 3D videos. In this paper, to give more fascinating viewing experience, constructing point-based models for 3D video processing in free-viewpoint TV is proposed. The results show the constructed models from two types of 3D videos. Furthermore, the subsequent processing can be benefited because the point-based model is compact and quite suitable for computer graphics techniques and the existing GPU hardware.
IEEE Transactions on Circuits and Systems for Video Technology | 2014
Yi-Nung Liu; Yi-Chun Lin; Yung-Lin Huang; Shao-Yi Chien
Because of real-time requirements and low hardware-cost constraints, conventional TV scalers can only employ basic interpolation technique and thus introduces some artifacts that degrade the viewing quality of the output sequences. In this paper, a low-complexity super-resolution (SR) algorithm, which can provide vivid output image with rich details and sharp edges, and its associated hardware architecture, is proposed. There are two main contributions in this paper. The first is the development of the database-free texture synthesis technique. With the fractal property of nature images, it is possible to find proper high-resolution patches in a low-resolution input image itself. Therefore, the texture synthesis can be performed without database to provide proper and rich details. In addition, a faithful reconstruction constraint is used to maintain the temporal consistency. The second contribution is the hardware architecture design of the database-free texture synthesis. Partial-sum reuse technique is developed to reduce 76% of computation in the texture synthesis, and a tile-based processing technique is proposed to dramatically reduce the on-chip memory and off-chip memory bandwidth requirements. Experimental results show that the proposed SR algorithm outperforms other ones with reasonable hardware cost, where 766k in gate count and 22 kB in on-chip SRAM are required to achieve full high-definition processing ability at the working frequency of 240 MHz. The results show that the proposed algorithm and architecture are able to provide high-quality output in real-time while solving the problems of zigzag and blurred effects caused by the conventional scalers.
signal processing systems | 2010
Yung-Lin Huang; Yi-Nung Liu; Shao-Yi Chien
Markov Random Field (MRF) has been successfully used to formulate the energy minimization problems in computer vision. However, a multi-label MRF model such as the conventional true motion estimation approach requires a significant amount of computation due to its large search space. Besides, we observe that decoding information obtained from H.264/AVC could be applied to reduce the computational complexity of true motion estimation. In this paper, a new true motion estimation scheme is proposed. We analyze the motion information and macroblock types from H.264/AVC decoder. According to the decoding information, predictors from the obtained motion vectors (MVs) are selected for MRF models. With these predictors, the search space of MRF could be reduced from O(n2) to O(n) compared to conventional full search scheme. Experimental results evaluated on the Middlebury optical flow benchmarks show that our proposed scheme is able to optimize the MV field of H.264/AVC decoder to approximate the true motion field.
IEEE Transactions on Circuits and Systems for Video Technology | 2017
Yung-Lin Huang; Fu-Chen Chen; Shao-Yi Chien
In current liquid crystal display (LCD) systems, the frame size becomes larger than the ultra-HD (
international conference on acoustics, speech, and signal processing | 2013
Ku-Chu Wei; Yung-Lin Huang; Shao-Yi Chien
3840\times 2160
international symposium on vlsi design, automation and test | 2012
Fu-Chen Chen; Yung-Lin Huang; Shao-Yi Chien
) resolution, and the refresh rate becomes higher than 120 Hz or more. However, the available video frame rates are usually at 24, 30, or 60 frames/s only, which are lower than the refresh rate of LCDs. To fill the gap between the video and LCD systems, frame interpolation techniques are usually adopted. Although frame rate up-conversion (FRUC) is regarded as the most efficient method, many design challenges are encountered in the current high-resolution and high-frame-rate LCD systems. In this paper, we developed a hardware-efficient multirate FRUC, which is capable of increasing the video frame rate from 24 or 60 to 120 frames/s. We improved the accuracy of motion vectors (MVs) between the video frames using predictive square search motion estimation (ME), followed by Markov random field (MRF) correction. Subsequently, we applied the block-based forward motion compensation (MC) to interpolate the intermediate frames. Thereafter, we performed subblock refinement to enhance the visual quality. The experiments show that the proposed algorithm performed well in both subjective and objective evaluations. We also designed hardware architecture for our multirate FRUC to support the current ultra-HD LCD systems. We proposed ping-pong two-way scheduling to eliminate the dependence among blocks. We realized 54%, 70%, and 35% cycle reduction and 62%, 82%, and 35% bandwidth reduction in the ME, MRF MV correction, and MC, respectively. The SRAM was shared by all modules, and its total size was reduced by 88%. We also implemented our design to a chip using the TSMC 90-nm cell library.
computer graphics international | 2016
Yen-Cheng Kung; Yung-Lin Huang; Shao-Yi Chien
Since most depth maps are quantized to 8-bit numbers in current 3D video systems, the induced cardboard effects can disturb human perception. Moreover, depth maps with larger resolution suffer more from the quantization error. Therefore, this paper proposes an optimization approach to reduce the depth quantization error with well-preserved structure of the depth maps. The experimental results demonstrate that the proposed approach can successfully recover the structure characteristics from the quantized depth maps. Evaluation in mean square error (MSE) and mean structural similarity index (MSSIM) also strongly support our theory and algorithm. Through enhancing the quality of the depth maps from the very beginning, this work can benefit most 3D processing applications, such as 3D modeling, shape registration, and view synthesis.
ieee global conference on signal and information processing | 2016
Po-Jen Lai; Yung-Lin Huang; Shao-Yi Chien
True motion estimation is a well-known technique to find the true object motion trajectory in a video, and it has a lot of applications in computer vision and display systems. However, if the target frame size becomes large, many new design challenges are introduced, such as huge computation, large bandwidth and large on-chip SRAM size requirements. Within the consideration of both algorithm and architecture, we develop a true motion estimator with ±128x±128 search range for video systems with Full-HD (1920×1080) resolution. The PSNR evaluation shows that our algorithm is better than other three existing algorithms. For hardware implementation, we use Verilog-HDL and synthesize it by SYNOPSIS Design Compiler with UMC 90nm cell library. The implementation works at 300MHz frequency, and it shows that there are total 76% bandwidth reduction, 66% cycle reduction and 88% on-chip SRAM reduction with the proposed ping-pong two-way scheduling and motion vector grouping techniques.
international conference on consumer electronics | 2015
Shang-Pu Fan; Yung-Lin Huang; Shao-Yi Chien
Surfaces are now where the augmented reality comes true. In this paper, we propose an efficient, learning-free and reliable way to detect for not only planar but also curved surfaces. Furthermore, our approach combines both advantages of local region growing and top-down refinements to retrieve wholesome surfaces in both organized point clouds and prebuilt 3D models. First, we obtain a down-sampled graph by supervoxel segmentation. Afterward, a recursive bottom-up agglomerative hierarchical clustering approach will iteratively merge the supervoxels into surfaces. Finally, top-down refinements on noisy and occluded planes will correct over-segmentations. To sum up, this is a model- and learning-free approach with experimental efficiency --- around 80 seeds and 3000 supervoxels are calculated for a 640x480 test point cloud, costing less than 0.2 sec on an ordinary laptop with 2.6GHz Intel core i5, 8GB RAM and without GPU aided.
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National Kaohsiung First University of Science and Technology
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