Yung-Yi Tu

Effects of initial GaN growth mode on the material and electrical properties of AlGaN/GaN high-electron-mobility transistors

AlGaN/GaN high-electron-mobility transistors (HEMTs) with different initial GaN growth modes were prepared on AlN/sapphire substrates. Secondary ion mass spectroscopy and Hall effect measurements confirmed that a highly conductive n-type region was generated at the GaN/AlN buffer interface during the three-dimensional to two-dimensional (3D–2D) growth mode transition. This n-type region was created by oxygen impurity incorporation during the 3D–2D growth mode transition, and its thickness increased with the transition time. The existence of this n-type conduction path not only changed the material properties but also degraded the device performance of HEMTs.

Investigation of electrical and thermal properties of multiple AlGaN/GaN high-electron-mobility transistors flip-chip packaged in parallel for power electronics

This paper demonstrates, for the first time, the potential of using flip-chip packaging to connect multiple AlGaN/GaN high-electron-mobility transistors (HEMTs) in parallel for application in power electronics. The electrical and thermal properties of both the bare and the packaged devices were experimentally investigated via pulsed current–voltage (I–V) measurements. Compared to the bare die, less than one-fifth the thermal resistance (Rth), triple the output current, and one-third the on-resistance (Ron) with temperature insensibility were observed when three transistors were connected in parallel through flip-chip packaging. Superior performance such as this makes flip-chip packaging a potential technology for high power GaN electronic applications.

Direct growth of a 40 nm InAs thin film on a GaAs/Ge heterostructure by metalorganic chemical vapor deposition

In this paper, the authors directly grew an InAs thin film (40 nm) by metalorganic chemical vapor deposition on GaAs/Ge substrates by using flow-rate modulation epitaxy with an appropriate V/III ratio. The growth of a high-quality InAs thin film with periodic 90° misfit dislocations was related to a uniform monolayer In atom distribution at the InAs/GaAs interface. The In monolayer effectively minimized the difference between surface energy and strain energy, producing a stable interface during material growth. The authors also found that a tightly controlled V/III ratio can improve the quality of the InAs islands on the GaAs/Ge heterostructures, though it is not the key factor in InAs thin-film growth.

Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect

We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.

Contact resistance reduction on layered MoS 2 by Ar plasma pre-treatment

The effect of resistance (Rc) reduction of Ti/Au contact on MoS2 by ICP Ar plasma pretreatment is presented. The lowest Rc of 1.72 ohm-cm was achieved with the ICP treatment condition of 50W (ICP) /2W (chuck) for 10 sec. Compared with the contact without treatment (19.6 ohm-cm), the Rc improves over 10 times, demonstrating the advantage of Ar plasma pre-treatment on MoS2 contact.

Wafer size MOS 2 with few monolayer synthesized by H 2 S sulfurization

Wafer sized, high quality continuous films would be a key demand for MoS<inf>2</inf> implemented in circuit application. In this study, the growth of few monolayer Mo<inf>S2</inf> on 4 inches SiO<inf>2</inf>/Si substrate were demonstrated. The MoS<inf>2</inf> thin films were synthesized by sulfurized in a furnace from the ultra-thin MoO<inf>3</inf> starting materials by using H<inf>2</inf>S. The obtained MoS<inf>2</inf> thin film examined by Raman analysis and Photoluminescence (PL), shows the semiconductor nature with direct transition peaks of 1.86 eV and 1.99 eV. The 4∼5 monolayer of MoS<inf>2</inf> with thickness around 2.6 nm is confirmed by cross-sectional view of transmission electron microscopy (TEM). Additionally, the DC characteristics of MoS<inf>2</inf> MOSFETs exhibit at least 2 order in on/off current ratio, demonstrating the feasibility for circuit application.

Synthesis of wafer-scale WSe 2 by WO x selenization on SiO 2 / Si substrates

Scalable synthesis of thin tungsten diselenide (WSe₂) films on 4-inch silicon substrate with 80 nm silicon dioxide (SiO₂) is demonstrated. Cross-sectional transmission electron microscopy (TEM) reveals good control of WSe₂ layers. Raman spectroscopy confirms high quality crystal of WSe₂ is achieved. Back-gated field-effect transistors (FETs) fabricated on these thin films exhibit p-channel characteristics with a good on/off current ratio larger than 1.2 × 10².

Post sulfurization effect on the MoS2 grown by pulsed laser deposition

Two inches size with high quality layered growth of MoS₂ was achieved by PLD on c-plane sapphire substrate. 2~3 monolayer MoS₂ was obtained within 2 inches wafer estimated from Raman analysis and confirmed by cross-sectional view of TEM. Additionally, the oxide states of Mo 3d core level spectra of MoS₂, analyzed by XPS, can be effectively reduced by adopting a post sulfurization process in H₂S. The post process also improve the photoluminescence (PL) of MoS₂ as well as the electrical characteristic of MoS₂ FET due to elimination the Mo oxide in the grown film.