Chun-Yen Yiu

3D device simulation of work function and interface trap fluctuations on high-κ / metal gate devices

This work, for the first time, examines the work function fluctuation (WKF) and interface trap fluctuation (ITF) using experimentally calibrated 3D device simulation on high-κ / metal gate technology. The random WKs result in 36.7 mV threshold voltage fluctuation (σVth) for 16 nm N-MOSFETs with TiN gate, which is rather different from the result of averaged WKF (AWKF) method [1] due to localized random WK effect. The ITF affects the subthreshold region (the normalized σID > 48%) and is suppressed for devices under strong inversion. Estimation of statistical covariance confirms the dependence of IT on the metal gates WK; thus, the impacts of WKF and ITF on device and circuit variability should be considered together properly. Such variability induced static noise margin fluctuation of SRAM exceeds the influence of random dopants and cannot be ignored.

A unified 3D device simulation of random dopant, interface trap and work function fluctuations on high-к/metal gate device

In this work, we for the first time estimate total fluctuation resulting from random dopants (RDs), interface trap (ITs) and work functions (WKs) using experimentally calibrated 3D device simulation on 16-nm-gate high-к/metal gate devices. The total 3D simulated threshold voltage fluctuation (σVth), induced by the aforementioned random sources simultaneously, is 55.5 mV for NMOS; however, a statistical total sum of these fluctuations is 12.3% overestimation because independence assumption on random variables is invalid owing to strong interactions among RDs, ITs and WKs. Devices DC/AC and CMOS SRAM circuit fluctuations have similar observation. FinFET-based structure innovation possessing large fluctuation suppression (σVth = 30.2 mV; 45.6% reduction), compared with process efforts on planar one, is further discussed.

Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal--Oxide--Semiconductor Field-Effect-Transistor Devices

In this work, we explore for the first time dual-material gate (DMG) and inverse DMG devices for suppressing the random-dopant (RD)-induced characteristic fluctuation in 16 nm metal–oxide–semiconductor field-effect-transistor (MOSFET) devices. The physical mechanism of suppressing the characteristic fluctuation of DMG devices is observed and discussed. The achieved improvement in suppressing the RD-induced threshold voltage, on-state current, and off-state current fluctuations are 28, 12.3, and 59%, respectively. To further suppress the fluctuations, an approach that combines the DMG method and channel-doping-profile engineering is also advanced and explored. The results of our study show that among the suppression techniques, the use of the DMG device with an inverse lateral asymmetric channel-doping-profile has good immunity to fluctuation.

Intrinsic parameter fluctuations on current mirror circuit with different aspect ratio of 16-nm multi-gate MOSFET

In this study, we examine the dependency of current mirror circuit characteristics on channel-fin aspect-ratio (AR = fin height / the fin width) of 16-nm multi-gate MOSFET and devices intrinsic parameter fluctuation including metal-gate work-function fluctuation (WKF), random-dopant fluctuation (RDF), process-variation effect (PVE), and oxide-thickness fluctuation (OTF). For n- and p-type current mirror circuits, the fluctuations dominated by RDF and WKF, respectively, could be suppressed by high AR of devices due to improved driving current. For n- and p-type current mirror circuits, IOUT fluctuation dominated by RDF and WKF in FinFET (AR = 2) is 2.8 and 2.5 times smaller than that of quasi-planar (AR = 0.5) device, respectively.

Large-scale statistical simulation of characteristic variation in 16-nm-gate Bulk FinFET devices due to work function fluctuation

We, for the first time, study the work-function fluctuation induced variability in 16-nm-gate bulk FinFET using an experimentally calibrated 3D device simulation. Random nanosized grains of TiN gate are statistically positioned in the gate region to examine the associated carrier transportation characteristics, concurrently capturing “grain number variation” and “grain position fluctuation.” The methodology of localized work-function fluctuation simulation enables us to estimate various characteristic fluctuations and to examine the random grains number and position effect for 16-nm-gate bulk FinFETs with TiN/HfO2 gate stacks with respect to the aspect ratio (AR = fin height/fin width).

Suppression of random-dopant-induced characteristic fluctuation in 16 nm MOSFET devices using dual-material gate

In this work, we for the first time explore the dual material gate (DMG) and inverse DMG devices for suppressing random dopant fluctuation (RDF)-induced characteristics fluctuation in 16-nm MOSFET devices. The physical mechanism of DMG devices to suppress RDF are investigated and discussed. The improvement of DMG for suppressing the RDF-induced Vth, Ion, and Ioff fluctuation are 28%, 12.3%, and 59%, respectively.

Electrical characteristic fluctuation and suppression in emerging CMOS device and circuit

We study the characteristic variability in high-к metal-gate CMOS device and circuit induced by various intrinsic fluctuation sources. Using an experimentally calibrated 3D device-and-circuit coupled simulation; we estimate the effect of metal-gate work-function fluctuation, oxide-thickness fluctuation, process-variation effect, and random-dopant fluctuation on device DC/AC characteristics. We then predict their impacts on transfer and dynamic properties of digital and analog circuits. Finally, variability suppression techniques are demonstrated from device engineering viewpoints.