Yungseon Eo

Silicon substrate coupling noise modeling, analysis, and experimental verification for mixed signal integrated circuit design

The frequency-variant characteristics of a silicon substrate were physically modeled, analytically investigated, and experimentally verified. The scalable circuit model parameter extraction methodology was newly developed. Thus, the proposed technique can provides the efficient performance evaluations as well as the accurate design guidelines concerned with the complicated mixed signal integrated circuit designs.

Signal Transient and Crosstalk Model of Capacitively and Inductively Coupled VLSI Interconnect Lines

Analytical compact form models for the signal transients and crosstalk noise of inductive- effect-prominent multi-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms of the equivalent transmission line model and transmission line parameters for fundamental modes. The signal transients and crosstalk noise expressions of two coupled lines are derived by using a waveform approximation technique. It is shown that the models have excellent agreement with SPICE simulation.

Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects

Novel signal integrity verification models for inductance-dominant RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multi-coupled line responses are decoupled into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combination of each eigenmode response based on TWA, followed by reporting the signal integrity models for the multi-coupled lines. The signal integrity of VLSI circuit interconnects has a strong correlation with input signal switching-patterns in the multiple lines. With the proposed analytic signal integrity models, the switching-dependent signal delay, crosstalk, ringing, and glitches of the inductance-dominant RLC interconnect lines can be accurately as well as efficiently determined. It is shown that the models have excellent agreement with SPICE simulations.

Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs

Analytical compact form models for the signal transient and crosstalk noise of two-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms with eigen modes (i.e., even mode and odd mode). The signal transients and crosstalk noise expressions of two coupled lines are derived by using a wave-form approximation technique for the modal signals. It is shown that the models have excellent agreement with SPICE simulation.

Experimental Characterization and Signal Integrity Verification of Interconnect Lines with Inter-layer Vias

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

Fast eye diagram determination for the signal integrity verification of frequency-variant transmission lines

A new efficient and accurate eye diagram determination technique is presented. In order to estimate the worst case eye diagram, bit streams which may induce the worst ISI (inter symbol interference) are determined. Then the output responses for worst case bit streams are determined by using fast Fourier transform technique. The proposed technique is compared with SPICE simulation that employs PRBS (pseudorandom bit sequence) input signals.

Timing Analysis of Discontinuous RC Interconnect Lines

In this paper, discontinuous interconnect lines are modeled as a cascaded line composed of many uniform interconnect lines. The system functions of respective uniform interconnect lines are determined, followed by its time domain response. Since the time domain response expression is a transcendental form, the waveform expression is reconfigured as an approximated linear expression. The proposed model has less than 2% error in the delay estimation.

Design and fabrication of a 10 Gb/s InGaAs/InP avalanche photodiode (APD) based on the non-local model

A 10 Gb/s APD is designed and fabricated by using the non-local model. Multiplication layer thickness and 2-dimensional Zn-diffusion profiles are optimized. The gain and bandwidth product (GB) more than 80 GHz, spatially uniform gain distribution, and the dark current less than 1 nA are successfully obtained.

Experimental via characterization for the signal integrity verification of discontinuous interconnect line

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process and measured using Vector Network Analyzer (VNA) up to 25 GHz. Then, by modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The circuit performance of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

Circuit modeling of Multi-Layer Ceramic Capacitors using s-parameter measurements

MLCC (multi layer ceramic capacitor) is characterized in the frequency range of 50 MHz to 20 GHz by using s-parameters. A test fixture that mounts an MLCC is designed with printed circuit board (PCB). Then the MLCC is characterized by using VNA and Impedance Analyzer. The circuit model parameters of the MLCC are extracted and its validity is verified.