Yunmo Koo

Strain-induced magnetoelectric coupling in BaTiO3/Fe3O4 core/shell nanoparticles

We report a strain-induced magnetoelectric coupling in BaTiO3/Fe3O4 ferroelectric core/ferrimagnetic shell nanoparticles. The temperature-dependent magnetoresistance and magnetization clearly show several jumps near the structural phase transition temperatures of BaTiO3. Below the Verwey transition temperature of Fe3O4, i.e., at 20 K, the dielectric constant of BaTiO3/Fe3O4 decreases continuously upon application of an external magnetic field, and the observed magnetodielectric curve does not follow the square of the magnetization. We discuss the effect of strain on the electric field-dependent magnetic anisotropy near the core/shell interface.

Nanoscale (∼10nm) 3D vertical ReRAM and NbO 2 threshold selector with TiN electrode

The scaling and 3-D integration issues of NbO₂ with threshold switching characteristics were investigated for ReRAM selector device. To avoid the process problems of Pt electrode, we tested ReRAM and selector devices with conventional electrodes (TiN and W). By adopting 10nm-thick TiN bottom electrode with low thermal conductivity, we could significantly reduce the threshold current for insulator-metal transition (I-M-T) due to the heat confinement effect. We have evaluated for the first time both 1S1R (NbO₂/TaO_x) and hybrid (NbO₂/Nb₂O₅) devices. We have confirmed the feasibility of high density vertical memory device by adopting NbO₂ I-M-T selector device.

Structurally Engineered Stackable and Scalable 3D Titanium‐Oxide Switching Devices for High‐Density Nanoscale Memory

A 3D high-density switching device is realized utilizing titanium oxide, which is the most optimum material, but which is not practically demonstrated yet. The 1S1R (one ReRAM with the developed switching device) exhibits memory characteristics with a significantly suppressed sneak current, which can be used to realize high-density ReRAM applications.

Effects of RESET Current Overshoot and Resistance State on Reliability of RRAM

Current overshoot has severe effects on the reliability of resistive random access memory (RRAM). It is well known that the current overshoot during the SET process is caused by parasitic capacitance. In this letter, we observed a different type of current overshoot during the RESET process. The RESET current overshoot was confirmed to have severe effects on the endurance of RRAM. We also demonstrated the relation between the current overshoot and the intrinsic capacitive elements of each state of RRAM. Finally, an optimized pulse shape was proposed to minimize the current overshoot and was experimentally verified to significantly improve the variability and endurance in a typical RRAM device with a W/Zr/HfO2/TiN structure.

Highly Reliable Resistive Switching Without an Initial Forming Operation by Defect Engineering

The effects of stack and defect engineering of metal-oxide layers on resistive switching uniformity were investigated to obtain resistive random access memory (ReRAM) with excellent switching reliability. Uniform switching, parameters, such as set voltage (Vset), reset voltage (Vreset), low-resistance state, high-resistance state, and retention characteristics, were significantly improved by stack and defect engineering. Furthermore, the initial forming operation, which is a nuisance, was removed to realize cross-point ReRAM.

Te-based amorphous binary OTS device with excellent selector characteristics for x-point memory applications

We demonstrated binary Ovonic threshold switching (OTS) materials (ZnTe, GeTe, and SiTe) and the composition dependent electrical properties. Among those materials, amorphous SiTe-film deposited at room-temperature (RT) process showed excellent OTS properties such as high off resistance (~20GΩ at 0.2V), low on resistance (<;1kΩ at 1.2V), high selectivity (~106), extreme SS (<;1mV/dec), fast operating speed (2ns transition after 10ns delay), and good endurance (>500k cycles). In addition, the origin of the electronic switching of the binary OTS device was examined.

Hardware implementation of associative memory characteristics with analogue-type resistive-switching device

We have investigated the analogue memory characteristics of an oxide-based resistive-switching device under an electrical pulse to mimic biological spike-timing-dependent plasticity synapse characteristics. As a synaptic device, a TiN/Pr0.7Ca0.3MnO3-based resistive-switching device exhibiting excellent analogue memory characteristics was used to control the synaptic weight by applying various pulse amplitudes and cycles. Furthermore, potentiation and depression characteristics with the same spikes can be achieved by applying negative and positive pulses, respectively. By adopting complementary metal-oxide-semiconductor devices as neurons and TiN/PCMO devices as synapses, we implemented neuromorphic hardware that mimics associative memory characteristics in real time for the first time. Owing to their excellent scalability, resistive-switching devices, shows promise for future high-density neuromorphic applications.

Tunnel barrier engineering of titanium oxide for high non-linearity of selector-less resistive random access memory

In this study, the effect of the oxygen profile and thickness of multiple-layers TiOx on tunnel barrier characteristics was investigated to achieve high non-linearity in low-resistance state current (ILRS). To form the tunnel barrier in multiple-layer of TiOx, tunnel barrier engineering in terms of the thickness and oxygen profile was attempted using deposition and thermal oxidation times. It modified the defect distribution of the tunnel barrier for effective suppression of ILRS at off-state (½VRead). By inserting modified tunnel barrier in resistive random access memory, a high non-linear ILRS was exhibited with a significantly lowered ILRS for ½VRead.

Electrical and reliability characteristics of a scaled (∼30nm) tunnel barrier selector (W/Ta 2 O 5 /TaO x /TiO 2 /TiN) with excellent performance (J MAX > 10 7 A/cm 2 )

We demonstrate a selector device with excellent performances (J_MAX > 10⁷A/cm², switching speed <; 20ns) at the 30nm cell size. Furthermore, these promising device characteristics were achieved in a fully CMOS compatible stack (W/Ta₂O₅/TaO_x/TiO₂/TiN) with extremely thin oxide layer (<; 10nm). Through the comprehensive understanding on the exponential I-V curve, the effect of intrinsic/extrinsic factors such as scaling (area and thickness), and parasitic components were systemically investigated.

Accelerated Retention Test Method by Controlling Ion Migration Barrier of Resistive Random Access Memory

Retention of the low resistance state (LRS) in resistive random access memory (ReRAM) significantly decreases at increasing electrical stress due to barrier lowering of ion migration and Joule heating. The LRS failure rate under externally applied bias could be modeled by adopting an Arrhenius equation for ion migration. Accelerated retention failure under voltage stress is explained by the combination of two effects: 1) lowering of the ion migration barrier by external electric field and 2) thermal energy enhancement through local Joule heating. Based on this model, an improved methodology for ReRAM data retention test is proposed, allowing to reduce the testing temperature and the experimental time by several orders of magnitude by applying a relatively low voltage.