Yunpeng Jia

Effect of grade doping buffer layer on SEE failure in VDMOSFET

Single event burnout (SEB) is a common single event effect (SEE) occur in VDMOSFET, previous studies have indicated the strong relationship between the devices secondary breakdown voltage and the SEB threshold voltage. This paper presents a grade doping buffer layer structure to improve the devices secondary breakdown voltage so that enhance the resistance to SEE. Through detailed simulation, it has been verified that optimized grade doping buffer layer can decrease the peak value of the electric field, significantly improve the parasitic bipolar turn-on current and the SEB threshold voltage. Moreover, compared to non-buffer layer and constant doping buffer layer structure, the optimized grade doping buffer structure is a more effective structure in SEE hardened VDMOSFET.

Micro-Raman spectroscopy applied in crystal structure analysis on the ESD failure mechanism of SiC JBS diodes

Abstract This paper propose a novel reliability analysis approach for electrostatic discharge (ESD) stress on 4H-SiC junction barrier Schottky (JBS) diodes using the technology of Micro-Raman spectroscopy. Several conventional analysis are firstly used to determine the failure site after the JBS diodes are destructed by ESD stress, including optical microscope (OM), Photoemission microscopy (PEM) and scanning electron microscopy (SEM). Then, the Micro-Raman spectroscopy is applied to analyze element identification and crystal structure of micro failure site. The analysis reveals that high electric field and high temperature concentrate in the high-voltage termination, resulting in diode burnout and changing the physical microstructure of base SiC. Furthermore, in the micro failure site, 4H-SiC with different Raman spectrum from base 4H-SiC are clearly found, and carbon escapes out from base SiC by combustion, leaving a mixture of amorphous silicon and polysilicon, which is decomposed from the base SiC on the failure surface.

Modeling for internal transparent collector IGBT

Internal transparent collector (ITC) insulated gate bipolar transistor (IGBT) is a new type IGBT. Its structure is quite similar to that of the PT-IGBT, but a very low carrier lifetime control region (LCLCR) is introduced in the collector region near the p-collector/n-buffer junction. In this paper, an analysis model for ITC-IGBT is proposed. The collector current density is given. It is function of carrier injected level, device physical parameters (carrier diffusion coefficient, diffusion length), and technology parameters (Doping level, base width, and position of LCLCR). The influence of the position of LCLCR, as well as carrier lifetime in it, on devices characteristics are discussed. For certain current density, if carrier lifetime in LCLCR is less than 0.01ns, and LCLCR is localized at 0.9µm away from base/collector junction, hole injection level decreases with temperature. Considering the mobility also decreases with temperature, devices on-state voltage VON will have positive temperature coefficient. The device is rugged; If carrier lifetime in LCLCR is about 1ns, and LCLCR is just under base/collector junction, the hole injection level increase with temperature. Even if the mobilitys decrease with temperature can not compensate the reduction of VON, the decrease degree of VON is much less than that of PT-IGBT. The device is more rugged than PT-IGBT. Optimum the position and carrier lifetime of LCLCR can make the device either rugged or less temperature sensitive (VON increase little with temperature). The position and carrier lifetime of LCLCR also plays important role for devices turn-off feature. When the position of LCLCR is settled, the lower carrier lifetime in LCLCR is, the shorter falling time will be. But when carrier lifetime in LCLCR is less than 10ps, the falling time is seldom influenced by the carrier lifetime in LCLCR. Further reduction of turn-off time can be obtained by reducing the distance of LCLCR to the collector/base junction.