Yury Audzevich

NetFPGA SUME: Toward 100 Gbps as Research Commodity

The demand-led growth of datacenter networks has meant that many constituent technologies are beyond the research communitys budget. NetFPGA SUME is an FPGA-based PCI Express board with I/O capabilities for 100 Gbps operation as a network interface card, multiport switch, firewall, or test and measurement environment. NetFPGA SUME provides an accessible development environment that both reuses existing codebases and enables new designs.

Efficient photonic coding: a considered revision

In this paper we reconsider the energy consumption of traditional DC-balanced physical line coding schemes applied to optical communication. We demonstrate that not only does an implementation of the popular 8B10B coding scheme have higher power consumption than the optical power requirement, but actually has higher power consumption when transmitting idle sequences than for real data packets. Furthermore, we show that simple codes retain the DC balance performance of 8B10B and hence do not increase the optical power requirement. We propose the use of a coding scheme that permits a default-off transmission system through the addition of a preamble. By analysis of trace data taken from a network covering a 24 hour period, we show that the power saving is up to 93%. The proposed approach not only enables energy proportional links but is fully compatible with future low power optical switched networks.

Power Optimized Transceivers for Future Switched Networks

Network equipment power consumption is under increased scrutiny. To understand and decompose transceiver power consumption, we have created a toolkit incorporating a library of transceiver circuits in 45-nm CMOS and MOS current mode logic (MCML) and characterize power consumption using representative network traffic traces with digital synthesis and SPICE tools. Our toolkit includes all the components required to construct a library of different transceivers: line coding, frame alignment, channel bonding, serialization and deserialization, clock-data recovery, and clock generation. For optical transceivers, we show that photonic components and front end drivers only consume a small fraction (<;22%) of total serial transceiver power. This implies that major reductions in optical transceiver power can only be obtained by paying attention to the physical layer circuits such as clock recovery and serial-parallel conversions. We propose a burst-mode physical layer protocol suitable for optically switched links that retains the beneficial transmission characteristics of 8b/10b, but, even without power gating and voltage controlled oscillator power optimization, reduces the power consumption during idle periods by 29% compared with a conventional 8b/10b transceiver. We have made the toolkit available to the community at large in the hope of stimulating work in this field.

Intelligent Energy-Aware Networks

Today the energy consumption of Information and Communication Technology (ICT) industry is a significant contributor to the total energy demand in many developed countries. Recent studies show that the ICT industry is responsible for about 2% of the global emission of CO2 and this percentage is predicted to increase as the Internet expands in bandwidth and reach. In this chapter we highlight different approaches for energy efficiency in communication networks. Firstly we review the techniques proposed to reduce the energy consumption of communication networks at the equipment and network levels. Secondly we investigate the use of renewable energy to reduce the CO2 emission of IP over WDM networks. Issues including how to use renewable energy (solar in this work) more effectively, how to reduce the nonrenewable energy consumption of transponders (the second most energy consuming device in a node), how to select the location of nodes using renewable energy, and load dependent energy consumption are considered. Thirdly we discuss workload migration using virtualization technologies in data centers as an approach of energy consumption minimization. Finally we consider some of the photonic systems advances which have the potential to reduce significantly the energy consumption within Ethernet switches and IP routers in the datacenter, showing how integrated photonic switch fabrics are starting to have the performance required for energy efficient high switching applications.This two-volume work levels both criticism and challenge to traditional developmental psychology. For too long, developmental psychologists have been studying individuals as if they developed in a sociocultural vacuum. As psychologists began to study the individuals development more broadly, they considered the impact of a number of other factors in the physical and social environment: early education, sociocultural differences, mass communication, alternative living arrangements, and medical care-to name but a few. Volume I, Historical and Cultural Issues, examines the problems of behavioral development from historical, political, theoretical, and cultural points of view. A number of content areas already familiar to developmental psychologists are discussed: Piagets theory, perceptual development, socialization, and language acquisition. In addition, topics relatively unfamiliar to American psychologists are included: the contribution of early European developmentalists such as William and Clara Stern, Alfred Binet, and Eduard Spranger; and an introduction to recent Soviet developmental theory. Volume II, Social and Environmental Issues, considers the effects of changes in social and environmental conditions upon individual development. The expanding impact of technology such as the communications media, the importance of nutrition, and the design of playgrounds and other spaces for growing children are among the changes examined, as are the impact of social organizations and interactions within small groups, focusing upon preschool education, interaction within the family, and personality development throughout the individuals life.

NetFPGA: Rapid Prototyping of Networking Devices in Open Source

The demand-led growth of datacenter networks has meant that many constituent technologies are beyond the budget of the wider community. In order to make and validate timely and relevant new contributions, the wider community requires accessible evaluation, experimentation and demonstration environments with specification comparable to the subsystems of the most massive datacenter networks. We demonstrate NetFPGA, an open-source platform for rapid prototyping of networking devices with I/O capabilities up to 100Gbps. NetFPGA offers an integrated environment that enables networking research by users from a wide range of disciplines: from hardware-centric research to formal methods.

Low power optical transceivers for switched interconnect networks

The power-consumption of network equipment is under ever-increasing scrutiny. As part of an ensemble project seeking to reduce power-consumption within data-centers1, this work focuses on reducing the power consumption of photonic transceivers for future fast power gated and/or optical switching networks. Utilising an open-source toolkit, we show that Serializer/Deserializer (SERDES) dominates power consumption of traditional optical transceivers. This result has particular implications for the modulation format of future interconnects. At 25 Gb/s line rate, SERDES blocks of PAM-16 and 4-wavelength WDM are shown to have 53% and 79% lower power respectively compared with SERDES of serial NRZ as well as reduced power gating restoration time and energy.

A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances

Network Function Virtualization (NFV) allows creating specialized network appliances out of general-purpose computing equipment (servers, storage, and switches). In this paper we present a PCIe DMA engine that allows boosting the performance of virtual network appliances by using FPGA accelerators. Two key technologies are demonstrated, SR-IOV and PCI Passthrough. Using these two technologies, a single FPGA board can accelerate several virtual software appliances. The final goal is, in an NFV scenario, to substitute conventional Ethernet NICs by networking FPGA boards (such as NetFPGA SUME). The advantage of this approach is that FPGAs can very efficiently implement many networking tasks, thus boosting the performance of virtual networking appliances. The SR-IOV capable PCIe DMA engine presented in this work, as well as its associated driver, are key elements in achieving this goal of using FPGA networking boards instead of conventional NICs. Both DMA engine and driver are open source, and target the Xilinx 7-Series and UltraScale PCIe Gen3 endpoint. The design has been tested on a NetFPGA SUME board, offering transfer rates reaching 50 Gb/s for bulk transmissions. By taking advantage of SR-IOV and PCI Passthrough technologies, our DMA engine provides transfers rate well above 40 Gb/s for data transmissions from the FPGA to a virtual machine. We have also identified the bottlenecks in the use of virtualized FPGA accelerators caused by reductions in the maximum read request size and maximum payload PCIe parameters. Finally, the DMA engine presented in this paper is a very compact design, using just 2% of a Xilinx Virtex-7 XC7VX690T device.

NetFPGA - rapid prototyping of high bandwidth devices in open source

The demand-led growth of datacenter networks has meant that many constituent technologies are beyond the budget of the wider community. In order to make and validate timely and relevant new contributions, the wider community requires accessible evaluation, experimentation and demonstration environments with specification comparable to the subsystems of the most massive datacenter networks. We demonstrate NetFPGA SUME, an open-source FPGA-based PCIe board for rapid prototyping of high bandwidth devices. NetFPGA SUME has I/O capabilities for 100Gbps operation as a networking device, computing unit, or for test and measurement.

Understanding PCIe performance for end host networking

In recent years, spurred on by the development and availability of programmable NICs, end hosts have increasingly become the enforcement point for core network functions such as load balancing, congestion control, and application specific network offloads. However, implementing custom designs on programmable NICs is not easy: many potential bottlenecks can impact performance. This paper focuses on the performance implication of PCIe, the de-facto I/O interconnect in contemporary servers, when interacting with the host architecture and device drivers. We present a theoretical model for PCIe and pcie-bench, an open-source suite, that allows developers to gain an accurate and deep understanding of the PCIe substrate. Using pcie-bench, we characterize the PCIe subsystem in modern servers. We highlight surprising differences in PCIe implementations, evaluate the undesirable impact of PCIe features such as IOMMUs, and show the practical limits for common network cards operating at 40Gb/s and beyond. Furthermore, through pcie-bench we gained insights which guided software and future hardware architectures for both commercial and research oriented network cards and DMA engines.