Yusaku Kashiwagi

Performance and reliability improvement in SiC power MOSFETs by implementing AlON high-k gate dielectrics

We have developed AlON high-k gate dielectric technology that can be easily implemented into both planar and trench SiC-based MOSFETs. On the basis of electrical characterization and numerical simulation, the thickness ratio of the AlON layer to the SiO2 interlayer and nitrogen content in AlON film were carefully optimized to enhance device performance and reliability.

Electrical improvement of CNT contacts with Cu damascene top metallization

We discuss the improvement in the electrical characterization and the performance of 150 nm diameter contacts filled with carbon nanotubes (CNT) and a Cu damascene top metal on 200mm wafers. The excellent agreement between the yield curves for the parallel and single contacts shows that a reliable electrical characterization is obtained. We demonstrate that integration changes improved the resistivity of the CNT contact significantly by reducing it from 11.8·10³ μΩ·cm down to 5.1·10³ μΩ·cm. Finally, a length scaling of the CNT contacts was used to find the individual contributors to the lowering of the single CNT contact resistance.

Electron mean-free path for CNT in vertical interconnects approaches Cu

A carbon nanotube (CNT) contact length scaling is used to derive the electron mean-free path (λCNT) after full integration. A CNT-to-metal contact resistance of 76 Ω and lower was obtained for 150 nm diameter contacts. By estimating the number of conducting walls in the CNT bundle, a λCNT of 74 nm is found, which is longer than for Cu. We propose a more conservative approach of calculating λCNT solely from electrical data. The result is that our CNT interconnects have ballistic transport over 24 nm, which is 5 times longer than reported so far.

Wafer-Level Electrical Evaluation of Vertical Carbon Nanotube Bundles as a Function of Growth Temperature

We have evaluated the resistance of carbon nanotubes (CNTs) grown at a CMOS-compatible temperature using a realistic integration scheme. The structural analysis of the CNTs by transmission electron microscopy (TEM) showed that the degree of graphitization decreased significantly when the growth temperature was decreased from 540 to 400 °C. The CNTs were integrated to form 150-nm-diameter vertical interconnects between a TiN layer and Cu metal trenches on 200 mm full wafers. Wafers with CNTs grown at low temperature were found to have a lower single-contact resistance than those produced at high temperatures. Thickness measurements showed that the low contact resistance is a result of small contact height. This height dependence is masking the impact of CNT graphitization quality on resistance. When benchmarking our results with data from the literature, a relationship between resistivity and growth temperature cannot be found for CNT-based vertical interconnects.

Electrical and structural characterization of 150 nm CNT contacts with Cu damascene top metallization

This paper discusses the electrical and structural characterization of 150 nm diameter contacts filled with carbon nanotubes (CNTs) and a Cu damascene top metal. We present the first images of CNTs in direct contact with the top metal. A CNT tip clean before metallization reduced the single CNT contact hole resistance from 4.8 kΩ down to 2.8 kΩ (aspect ratio 2.4). The first basic electrical breakdown experiments with Kelvins resulted in high breakdown currents of 5-13 MA/cm2.

Reliability-aware design of metal/high-k gate stack for high-performance SiC power MOSFET

Advanced metal/high-k gate stack technology for SiC-based power MOSFET was demonstrated. We found that the Hf incorporation into aluminum oxynitride (HfAlON gate insulator) combined with TIN electrode effectively improves the stability of threshold voltage under both negative and positive bias temperature stresses. Since the relative permittivity of HfAlON increases with increasing Hf content, peak transconductance enhancement up to 3.4 times with acceptable reliability margin was achieved in the state-of-the-art trench MOSFET by implementing TiN/HfA10N(Hf50%) gate stack.

Flatband Voltage Shift Depending on SiO2/SiC Interface Charges in 4H-SiC MOS Capacitors with AlON/SiO2 Stacked Gate Dielectrics

The mechanism of flatband voltage shift in SiC metal-oxide-semiconductor (MOS) capacitors with stacked gate dielectrics consisting of aluminum oxynitride (AlON) layers and SiO2 underlayers was investigated by varying the AlON and SiO2 thicknesses. The flatband voltages of the fabricated capacitors with fixed SiO2 underlayer thicknesses were almost independent of the AlON thickness, indicating the negligible charges in AlON layer. On the other hand, when varying SiO2 underlayer thickness, the flatband voltage decreased with an increase in capacitance equivalent thickness (CET), and the slope of their linear fit was comparable to that for SiC MOS capacitors without AlON layer. These observations can be well explained by assuming interface charges at AlON/SiO2 interface with an amount comparable, but a polarity opposite to, those at SiO2/SiC interface.