Yutaka Kumano

Development of chip-on-flex using SBB flip-chip technology

Abstract A bare LSI chip mounted onto a flexible substrate is called chip-on-flex (COF). Companies and universities are desperately developing COF. In this paper, the development of COF using stud bump bonding (SBB) flip-chip technology will be introduced. So far, SBB technology has been adopted when ceramic or glass-epoxy is used as a substrate material for chip size packages (CSPs) and multi-chip modules (MCMs). Recently there is a great demand for developing SBB technology toward a flexible substrate. SBB technology needs to keep a flexible substrate flat during the assembly process. A flexible substrate was adhered to a flat carrier using a thermal release sheet in order to keep it flat. Since this thermal release sheet loses its adhesive strength by applying heat beyond 160°C, it is easy to peel off accomplished specimens from the flat carrier after assembling. SBB specimens were prepared using liquid crystal polymer (LCP) and polyimide (PI) as a flexible substrate. Reliability tests, such as pressure cooker test (PCT), thermal shock test (TST) and reflow soldering after moisture storage test, were carried out for these specimens. In PCT, both LCP and PI specimens passed as a result of using proper underfill for each substrate. In TST, both specimens also passed using the underfill selected in PCT. In reflow soldering after moisture storage test, LCP specimens passed, on the other hand PI specimens needed to be baked after moisture storage in order to pass the reflow.

High-Accuracy Thermal Analysis Methodology for Semiconductor Junction Temperatures by Considering Line Patterns of Three-Dimensional Modules

A novel computational fluid dynamics analysis method of predicting semiconductor junction temperatures precisely without modeling printed circuit board (PCB) line patterns was developed. First, PCBs are divided into multiple regions. The effective anisotropic thermal conductivity of each region is then assigned as follows. All the regions are divided into smaller subregions whose size is below the pattern width. The thermal conductivity of each subregion is defined by the property of the material at the center of the subregion. Next, a thermal circuit network composed of all the subregions is generated, and finally the anisotropic thermal conductivities of each region are computed by solving this thermal network matrix. When boards are divided into multiple regions, there is a convergence region size under which the analytical results show no further change. In this paper, the relationship between the size of the divided regions and the accuracy of the analytical results was investigated. It was confirmed that the calculated semiconductor junction temperatures were precisely coincident with the experimental results when the size of the regions was less than 20 times the line pattern width.

High Accuracy Thermal Analysis Methodology for Semiconductor Junction Temperatures Considering Line Patterns of Multilayered Circuit Boards

As multilayered circuit boards in which semiconductors are embedded have been well reported, thermal management is becoming quite an important issue. In order to predict the junction temperature of an embedded semiconductor precisely, it is necessary that line patterns should be taken into consideration for thermal fluid analysis. However modeling all the patterns correctly is unacceptable because of far too long calculation time. Thus only the ratio of a pattern area to a gross board area was considered, which caused up to 30% calculation error compared to the experimental results. We have developed a novel method to predict semiconductor junction temperatures precisely without modeling patterns themselves. Firstly boards are divided into multiple regions in order to express how much dense or coarse the patterns are. Since the size of each region is much larger than L/S (line and space) specification of the boards, the number of meshes for calculation does not increase explosively and the simulation can be finished within appropriate time. Secondly equivalent anisotropic thermal conductivity of each region is assigned as follows. All the regions are once divided into smaller subregions whose sizes are approximately L/S specification. Then thermal conductivity of each subregion is defined by the property of the material at the centered subregion. After that a thermal network composed of all the subregions is generated and anisotropic thermal conductivities of each divided region are computed by solving this thermal network matrix. This procedure should be executed in an electrical CAD (E-CAD) where line pattern data are stored. A new interface format using which we can transfer board data from E-CAD to thermal fluid simulator was prepared. This format can have not only layouts and sizes but also anisotropic thermal conductivities of all divided regions. There is no need either to prepare model geometries or to input attributes of a great number of divided regions on thermal fluid simulator. By way of this format, analytical models are imported in thermal fluid simulator and semiconductor junction temperatures are computed. It was confirmed that semiconductor junction temperatures calculated by this method were precisely coincident with the experimental results. We can predict semiconductor temperatures without making preproduction samples. This analysis methodology will highly contribute to the reduction of designing time and cost.Copyright