Minehiro Itagaki

Development of chip-on-flex using SBB flip-chip technology

Abstract A bare LSI chip mounted onto a flexible substrate is called chip-on-flex (COF). Companies and universities are desperately developing COF. In this paper, the development of COF using stud bump bonding (SBB) flip-chip technology will be introduced. So far, SBB technology has been adopted when ceramic or glass-epoxy is used as a substrate material for chip size packages (CSPs) and multi-chip modules (MCMs). Recently there is a great demand for developing SBB technology toward a flexible substrate. SBB technology needs to keep a flexible substrate flat during the assembly process. A flexible substrate was adhered to a flat carrier using a thermal release sheet in order to keep it flat. Since this thermal release sheet loses its adhesive strength by applying heat beyond 160°C, it is easy to peel off accomplished specimens from the flat carrier after assembling. SBB specimens were prepared using liquid crystal polymer (LCP) and polyimide (PI) as a flexible substrate. Reliability tests, such as pressure cooker test (PCT), thermal shock test (TST) and reflow soldering after moisture storage test, were carried out for these specimens. In PCT, both LCP and PI specimens passed as a result of using proper underfill for each substrate. In TST, both specimens also passed using the underfill selected in PCT. In reflow soldering after moisture storage test, LCP specimens passed, on the other hand PI specimens needed to be baked after moisture storage in order to pass the reflow.

Development Of Zero X-y Shrinkage Sintered Ceramic Substrate

Studies of multilayered ceramic substrate are made briskly ,which makes it possible to design wiring patterns high densely and to mount bare IC chips. The multilayered cbramic substrate is expected for effectiveness for high functional, downsizing and confidential devices. In order to realize high density ceramic Multi-Chip-Module (MCM), multilayered ceramic substrate is required to satisfy demands for fine patterning, small packaging and low cost, Especially, sintering shrinkage of a substrate should be. controlled for fine patteming. Generally, the ceramic substrate undergoes its shrinkage of 10 to 15% and the shrinkage error is *OS%, so the substrate is not suitable for mounting bare IC chips. On considering of such problem, zero X-Y shrinkage sintered ceramic substrate (ZSS) has been developed by the conventional green sheet method, which arranges substrate green sheets between two no-shrinkage sheets, horizontal shrinkage during sintering is prevented to 0.18, and the shrinkage error i s f 0.05%. In this paper, we will report a material, process for prohibiting the horizontal shrinkage and properties of ZSS. .

Packaging properties of ALIVH-CSP using SBB flip-chip bonding technology

A new chip scale package (CSP) using an organic laminated substrate (CSP-L) was developed, which was fabricated using an ALIVH (any layer inner via hole) substrate as an interposer and stud-bump-bonding (SBB) flip-chip technology. The ALIVH substrate is a multilayered organic substrate with inner via holes in any layer. The newly developed CSP-L using the ALIVH substrate realized package size miniaturization on the same scale as a CSP using a ceramic substrate (CSP-C). The SBB flip-chip bonding on the ALIVH substrate required an excellent substrate surface coplanarity. The required coplanarity was obtained using a fixture during the SBB flip-chip bonding process. The first-level packaging reliability and the second-level packaging reliability on a glass-epoxy motherboard were evaluated. The resulting reliabilities were good enough for practical applications.

High frequency performance of integral capacitors in cofired ceramic substrates

Impedance measurements for an integral capacitor in GHz range up to 9 GHz has been achieved with resonant method using coaxial resonators. Two open-ended coaxial resonators were used in this resonant method. The one was reference and the other was target whose length was the same as that of the reference. The difference between the reference and target was that a device under test was located in the center of the reference resonator. The ESL and ESR were calculated from differences of the resonant frequencies and quality factors between reference and target resonators. The characteristics of the integral capacitor with BCN or BCZN as dielectric materials in the zero x-y shrinkage LTCC substrate were measured. We confirmed that the ESL was determined by the dimension of the capacitor and the ESR was determined by the electrode configurations. We also confirmed that the ESL and ESR of the integral capacitor were very small and these integral capacitors were good enough to be applied in high frequency circuits at least up to 9 GHz.

A zero X-Y shrinkage low temperature cofired ceramic substrate using Ag and AgPd conductors for flip-chip bonding

A zero X-Y shrinkage low temperature cofired ceramic (LTCC) substrate was developed, that was applied to the flip-chip bonded chip-size-packages (CSPs) and multi-chip modules (MCMs). The Ag internal conductor,the AgPd external conductor and the newly developed Ag via conductor could be used by matching the sintering shrinkage behavior with that of the zero X-Y shrinkage LTCC substrate. The flip-chip bonding using stud-bump-bonding (SBB) technique could be performed onto the external conductor of this developed substrate without Au plating and stable flip-chip bendability was obtained.