Yuuichiro Mitani

Tunneling current modulation by Ge incorporation into Si oxide films for flash memory applications

Current-voltage characteristic for a Ge-incorporated Si oxide was investigated. Current enhancement was observed for the electric field larger than 10 MV/cm. Such a current enhancement only under high electric field is expected to improve programming performance without deteriorating reading performance. From secondary ion mass spectrometry and hard x-ray photoelectron spectroscopy analyses and current simulation, it is concluded that the Ge impurity in Ge4+ state around the tunnel oxide/substrate interface enhances the current by trap-assisted tunneling. The programming current enhancement induced by the Ge incorporation is expected to be one of the promising solutions for the next-generation flash memory.

Comprehensive investigations on neutral and attractive traps in random telegraph signal noise phenomena using (100)- and (110)-orientated CMOSFETs

Neutral traps and attractive traps in random telegraph noise (RTN), on both (100)- and (110)-orientated CMOSFETs, are well distinguished and systematically studied for the first time, including both electron and hole traps. It is found that neutral traps energy distributions are higher than attractive traps and, most importantly, neutral traps caused much larger threshold voltage shifts (ΔVth_RTN) than attractive traps do, especially in (110)-nMOSFETs. Furthermore, based on obtained ΔVth_RTN in CMOSFETs on surface of various orientations, 3D structure optimizations are discussed in view of ΔVth_RTN suppression.

Impact of trap creation at SiO 2 /Poly-Si interface on ultra-thin SiO 2 reliability

The relationship between TDDB characteristics of the devices having ultrathin SiO2 as gate dielectrics and the hydrogen-related trap creation have been re-investigated from the viewpoint of the oxidation process dependence. In order to study the influence of hydrogen on the reliability, deuterium isotope effect has been used. As a result, the Weibull distributions of time-to-breakdown (tBD) depends on the oxidation process condition even under the same oxidation temperature. Trap creation at gate oxide interface strongly correlates to the dielectric breakdown in ultra-thin gate oxides However, this oxidation process dependence could not be explained only by the amount of hydrogen release from SiO2/Si substrate interface From the experimental results of low-voltage SILC, it can be concluded that not only the released hydrogen from SiO2/Si substrate interface but also those from Poly-Si/SiO2 interface correlates to the breakdown mechanisms.

Understandings on Surface Orientation Impacts on Random Telegraph Signal Noise Related Carriers Trapping Time Constants and Current Fluctuations

Random telegraph signal (RTS) noise in (110)and (100)orientated nMOSFETs are studied systematically, with main focuses on surface orientation impacts on carrier trapping time constants and traps induced channel current fluctuations. On the one side, single trap’s RTS noise and multiple traps’ RTS noise are all evaluated to estimate current fluctuations (∆Id/Id) and threshold voltage shifts (∆Vth). It is observed that ∆Id/Id and ∆Vth degradations are much more serious in (110) nFETs. On the other side, couplings between time constants and applied gate biases are compared. Traps in (110) nFETs illustrate much stronger couplings than in (100) nFETs, which might related to various trap positions and inversion electron distributions. Correlations between current fluctuations and couplings are also discussed for further understandings. Introduction Along with development of scaling-down techniques, device structures are changed from traditional flat structures to three dimensional (3D) structures. Accordingly, in order to improve device performances with higher carrier mobility and steeper sub-threshold slopes, structure optimizations have been studied systematically [1]. Simultaneously, how to suppress reliability degradation in small area devices, like worse RTS noise, is also important. Studies on RTS noise have been continued for a long time and intensively reported in last few years because its serious impacts in scaling-down devices and circuits can not be ignored anymore, such as CMOS image sensors [2] and NAND flash memories [3]. Accordingly, finding acceptable balances between performances and reliabilities by optimizing structures is believed to be critical from now on. It was used to be reported that performances in (110) nFETs are approaching to those in (100) nFETs as scaling down [4], while experiment work on RTS noise comparison between (110) and (100) devices are still limited [5]. In this work, impacts of surface orientations on RTS noise are systematically studied in both (100) nFETs and (110) nFETs, including trap time constants and carrier trapping induced fluctuations (∆Id/Id, ∆Vth). On the one hand, it is found that couplings between time constants and gate biases are stronger in (110) nFETs; on the other hand, ∆Id/Id and ∆Vth degradations are much more serious in (110) FETs. Physical mechanisms on correlations between time constant couplings and fluctuation amplitudes are also discussed for further understandings. Experimental Results and Discussions A. RTS noise characterization methods RTS noise are studied and compared in (110) nFETs and (100) nFETs with identical 2nm gate oxide, by using Agilent B1530 RTS noise characterization system. Channel doping concentration (Nch) ranges from 2E17cm -3 to 2E18cm -3 . Typical RTS phenomena due to one and two traps are illustrated respectively in Fig. 1(a). For single trap, detail information of time constants can be extracted, such as time to capture (τc), time to emission (τe), and time constant couplings on the gate bias Vg (ατe, ατc, ατe/τc), as shown in Fig. 1(b). For multiple traps, though time constants of each trap are difficult to be extracted, histogram graph of drain currents or time lag plot (PLT) [6] can be utilized to estimate trap numbers as well as ∆Id/Id. So, surface orientation impacts on trap density can be qualitatively studied. (a) (b) Fig.1 (a) Observation of typical RTS noise, single trap induced two Id levels and two traps induced four Id levels; (b) extracted time constants from single trap RTS noise, τc, τe and τc/τe. (a) 0 0.5 1.0 1.5 2.0 0.0% 0.1% 0.2% (110) nFETs

Experimental proof of direct correlation between hydrogen migrated to SiO 2 /Si interface and MOSFET characteristics using high energy 15 N 2+ ion beam

High energy 15 N 2+ ion beam was used not only as NRA (Nuclear Reaction Analysis) for the estimation of hydrogen depth profile but also as the measure to migrate hydrogen to the SiO2/Si interface. In the case of SiO2 formed by wet oxidation (WO), the leakage current and interface trap density (Nit) were dramatically degraded after ion beam irradiation due to the depassivation of hydrogen in the bulk followed by hydrogen migration to the interface. As for SiO2 formed by radical oxidation (RO), the significant hydrogen migration to the interface was not observed and the increased Nit value was almost the same as that of constant current stress case. The direct correlation between hydrogen at the interface and MOSFET degradation was successfully demonstrated.

Comprehensive Understandings on Reliability Modulations in Compressive Stressed (100)- and(110)-Orientated Silicon CMOSFETs

1. Abstract: Compressive stress impacts on reliabilities in both (100)and (110)-orientated CMOSFETs were studied systematically. It was interesting to found that, longitudinal compressive stress helps to obtain better NBTI performance in both (100) and (110) pMOSFETs. Also, along with transverse compressive stress increasing in narrow pMOSFETs, better NBTI performance can also be obtained in (110) pMOSFETs, though NBTI degradations was observed in (100) pMOSFETs due to worse STI edges. Furthermore, together with SILC and TDDB characterizations, it is concluded that compressive stress can modulate dielectric/channel interface states and achieve better NBTI performances, while it weakly affects bulk dielectric properties. Underlying physical mechanisms are discussed. 2. Introductions: Along with CMOS scaling down technologies, reliability in stress-engineered devices attracts more and more attentions. It is known that better initial interface qualities can be obtained by dangling bonds passivation [1], while excessive hydrogen will degrade dielectric reliability on the contrary, as reported in pMOSFETs with compressive SiN film as contact etch stopper layer (CESL) [2]. Also, it was observed that, with CESL compressive stress films, reliability can be improved in both nand pMOSFETs [3]. So far, stress effects on reliability are mainly studied in MOSFETs with additional stress films or mechanical stressors, but reliability dependence on intrinsic stress, such as layout-induced stress, are easily screened. In this work, in order to decouple intrinsic stress effects from additional stress film effects screening, both (100) and (110) CMOSFETs are studied and compared, by utilizing layout-induced compressive stress. For further understandings, carrier mobility, NBTI, SILC and TDDB are characterized and compared and discussed. It is interesting to found that, though bulk dielectric properties weakly dependents on compressive stress, better NBTI properties were observed in compressively stressed (100) and (110) pMOSFETs. 3. Measurement Results and Discussions: Firstly, carrier mobility was characterized to confirm layout induced stress effects [4]. Fig. 1 is layout of studied MOSFETs and TEM images in wide and narrow MOSFETs. Figs.2 and 3 shows measured mobility in (100) and (110) MOSFETs with dependence on Lg and Wg, respectively. In (100) MOSFETs, mobility degradation in short and narrow nMOSFETs are larger than that in pMOSFETs. Comparisons between devices of various Xg were shown in Fig.4. On (100) surface, smaller Xg causes hole mobility enhancements but electron mobility degradations. Mobility modulations strongly indicate the existence of compress stress [4]. In other words, devices with short Lg but same Xg accept stronger longitudinal compressive stress due to smaller active area lengths Lg+2Xg. Observed carrier mobility modulations in Figs.2~4 can be explained well by considering layout-induced compressive stress. Also, gate leakage (Jg) modulations were measured. Due to compressive stress effects [5-6], Jg increases in (110) nMOSFETs of smaller Xg while decreases in pMOSFETs. Measured Vth, Jg and μeff are summarized in Table I for reference. Then, interface states were characterized by using charge-pumping (CP) method. Based on extracted Wg dependence of Icp in Fig. 5, it is found that, Dit at (100) interface has large degradations as shrinking Wg, which can be explained by larger contributions from worse STI edge [7]. However, Dit at (110) interface has weak Wg dependence due to originally worse Si/SiO2 interface. Next, reliability properties were characterized systematically. As shown in Fig. 6, in (100) pMOSFETs, worse NBTI is observed in narrow channel devices, which agrees with worse Dit (Fig.5). However, NBTI is surprisingly improved in narrow (110) pMOSFETs. Opposite Wg dependence on (100) and (110) pMOSFETs can be clearly distinguished in Fig. 7. Then, NBTI are measured in devices of various Xg. As longitudinal compressive stress increases with Xg shrinking, better NBTI are observed in both (100) and (110) pMOSFETs (Fig. 8), indicating that better NBTI originates from larger compressive stress. Stress induced leakage current (SILC) is characterized in devices of various designs to study stress effects on bulk dielectric properties, as shown in Fig. 9, however, there is no obvious difference in all studied devices. Time dependent dielectric breakdown (TDDB) properties are measured in rectangular capacitors of 1um and 0.5um side length. Similarly, there is no difference in Weibull distributions (Fig. 10). In summary, layout-induced stress results in improved NBTI but has weak effects on the quality of bulk dielectrics (Fig. 11). It deserves to be noted here, different from previous work [1-3], there is no additional stress film in studied devices and proposed CESL stressing layer impacts in [3] can not explain observed better NBTI performance in this work. Nevertheless, since compressive stress from shrinking gate-to-STI distances previously existed before gate oxidation, it is believed that interface states creations during gate oxidation can be affected by initially existed surface stress states [8]. Also, according to two stage model in [9], Si-Si at SiO2 side should break before Si-H breaking. Thus, though initial states are almost identical, Si-H at stressed Si/SiO2 interface is difficult to break due to stronger Si-Si bonding, and less Si-H breaking results in better NBTI performances. 4. Conclusions: Systematical investigations were done for comprehensive understandings on layout-induced stress effects in CMOSFETs reliability. It is interesting to found that, in both (100) and (110) pMOSFETs, longitudinal compressive stress results in better NBTI. However, with stronger transverse compressive stress, better NBTI can be only obtained in (110) pMOSFETs, but NBTI degradations were observed in (100) pMOSFETs due to worse STI edge impacts. Also, layout induced stress has weak effects on SILC and TDDB performances. Suppressed Si-H breaking at compressively stressed interface is considered to explain observed phenomena. This work indicates that stress engineering, as both performance and reliability booster, is an important candidate for future CMOS technology.

Influence of channel area scaling on Weibull distribution of TDDB for poly-Si channel FET

Introduction Three-dimensional (3D) integration technology has attracted much attention since it gives rise to the higher packing density, shorter interconnection, lower power consumption and heterogeneous device integration[1]. Recently, 3D-FPGA using TFT configuration SRAM over bulk CMOS logic was proposed[2]. Furthermore, it has been reported that the mobility and ON/OFF current of TFT are dramatically improved when the channel area reduces comparable to the grain size[3]. Therefore, the scaled poly-Si channel transistor in combination with high-performance CMOS device is a promising technology to overcome the conventional CMOS scaling limitation. However, long-term reliability, especially the statistical distribution of reliability, of poly-Si channel FET with small area has not been clarified yet. In this paper, by focusing on the statistical distribution of TDDB for the gate oxide grown on poly-Si with large and small channel area comparing to that on the conventional Si(100) surface, we discuss the guideline in the reliability of gate oxide on poly-Si channel.

Programming Current Enhancement by Ge Incorporation into Tunnel Oxide Film

Corporate Research and Development Center, Toshiba Corporation 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan Phone: +81-44-549-2119 Fax: +81-44-520-1501 E-mail: toshihide1.ito@toshiba.co.jp Corporate Manufacturing Engineering Center, Toshiba Corporation 33, Shinisogo-cho, Isogo-ku, Yokohama 235-0017, Japan Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan