Kosuke Tatsumura

Diffusion and activation of n-type dopants in germanium

The diffusion and activation of n-type impurities (P and As) implanted into p-type Ge(100) substrates were examined under various dose and annealing conditions. The secondary ion mass spectrometry profiles of chemical concentrations indicated the existence of a sufficiently high number of impurities with increasing implanted doses. However, spreading resistance probe profiles of electrical concentrations showed electrical concentration saturation in spite of increasing doses and indicated poor activation of As relative to P in Ge. The relationships between the chemical and electrical concentrations of P in Ge and Si were calculated, taking into account the effect of incomplete ionization. The results indicated that the activation of P was almost the same in Ge and Si. The activation ratios obtained experimentally were similar to the calculated values, implying insufficient degeneration of Ge. The profiles of P in Ge substrates with and without damage generated by Ge ion implantation were compared, and it ...

Intrinsic correlation between mobility reduction and V t shift due to interface dipole modulation in HfSiON/SiO 2 stack by La or Al addition

Intrinsic correlation between mobility reduction by remote Coulomb scattering (RCS) and threshold voltage shift (DeltaVt), both of which are induced by interface dipole modulation at high-k/SiO2 interface, is investigated. Three types of dipole modulation are examined; Al addition, La addition, and changing quality of interfacial SiO2 layer. Extrinsic scattering components due to increases of interface state and surface roughness are extracted and separated. It is found that RCS due to interface dipole modulation by Al addition increases with increasing DeltaVt, while that by La addition is constant, independent of DeltaVt. Inevitability of additional scattering for DeltaVt is discussed based on two different models for dipole formation mechanisms.

Novel V TH self-adjusting MISFET with SiN charge trap layer for ultra low power LSI

A novel V<inf>TH</inf> self-adjusting FET with SiN charge trap layer is proposed and experimentally demonstrated. The V<inf>TH</inf> self-adjusting FET has a poly Si/SiN/SiO<inf>2</inf>/Si gate stack and can be introduced to conventional CMOS platform with a small additional cost. The |V<inf>TH</inf>| of the V<inf>TH</inf> self-adjusting nFET and pFET decrease on on-state and come back to the initial high value on off-state due to charging and neutralization of the SiN layer by exchange of electrons with gate electrode. The dynamic V<inf>TH</inf> tuning ability improves both of read and write margins of SRAM. V<inf>TH</inf> tuning ability of 100mV is achieved by Si-rich SiN film of less than 1nm, which leads to reduction of minimum operating voltage (V<inf>DD_min</inf>) of SRAM by 170mV. It is found that switching energy efficiency (energy per a cycle) can be improved largely beyond the limit of conventional FET in ultra low V<inf>DD</inf> region by V<inf>TH</inf> self-adjusting function.

Correlation between low-field mobility and high-field carrier velocity in quasi-ballistic-transport MISFETS scaled down to L g =30 nm

Mobility (μ) and L<inf>g</inf> dependence of high-field velocity (v) is systematically investigated. A wide variety of μ characteristics are realized with various gate dielectrics of SiO<inf>2</inf>, SiON, HfLaSiON, and HfLaAlSiON. At L<inf>g</inf>=30nm, the sensitivities of v to μ and scaling in L<inf>g</inf>, (δv/v)/(δμ/μ) and (δv/v)/(δL<inf>g</inf>/L<inf>g</inf>), are 0.43 and −0.45, respectively: in quasi-ballistic transport regime, μ and scaling in L<inf>g</inf> still play an important role on I<inf>on</inf> improvement with v enhancement. High-k MISFETs do not show any particular v degradation in high-energy carrier transport. μ-T<inf>inv</inf> characteristics of MG/high-k gate-stacks required for 22nm-node and beyond is discussed based on the experimental data for μ and L<inf>g</inf> dependence of v.

Impact of tantalum composition in TaC/HfSiON gate stack on device performance of aggressively scaled CMOS devices with SMT and strained CESL

We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a dominant factor to improve device performance. By optimizing TaCx composition, fixed charge free TaCx/HfSiON device is successfully fabricated. Also, we have demonstrated that the strain effect in deeply scaled devices can be enhanced by eliminating the fixed charges in HfSiON, for the first time. Utilizing Stress Memorization Technique (SMT) and strained Contact Etch Stop Layer (CESL), Lg = 35 nm high performance TaCx/HfSiON devices is achieved.

Nonvolatile Programmable Switch With Adjacently Integrated Flash Memory and CMOS Logic for Low-Power and High-Speed FPGA

Novel nonvolatile programmable switch for low-power and high-speed field-programmable gate array (FPGA) where flash memory is adjacently integrated to CMOS logic is demonstrated. The flash memory and the high-speed switching transistor (SwTr) are fabricated close to each other without deteriorating their respective performance. Furthermore, programming schemes to write and erase the flash memory are optimized so that the memory is successfully programmed without any damage to the SwTrs. Flash-based configuration memory in the nonvolatile programmable switch has only half the area of the conventional static random-access memory-based one, and it can be placed in each block in FPGA, enabling efficient power gating that offers low-power FPGA operation.

Flash-based nonvolatile programmable switch for low-power and high-speed FPGA by adjacent integration of MONOS/logic and novel programming scheme

Novel nonvolatile programmable switch for low-power and high-speed FPGA where MONOS flash is adjacently integrated to CMOS logic is demonstrated. The MONOS transistors (MTrs.) and low-voltage switching transistors (SwTrs.) are fabricated close to each other without deteriorating each performance. Furthermore, memory programming scheme is optimized to realize selective writing with no damage in the SwTrs. MONOS-based configuration memory has a half area of conventional SRAM, and it can be placed in each block in FPGA. That enables efficient power gating (PG) that offers low-power FPGA operation.

X-ray diffraction study of strain distribution in oxidized Si nanowires

Strain distributions in oxidized Si nanowires fabricated on a (001)-oriented silicon-on-insulator wafer have been determined by analyzing intensity profiles of the diffraction, caused by the nanowire periodicity, around the 111 Bragg point. In this analysis, theoretical diffraction curves, calculated by a kinematical treatment, are fitted to experimental ones, examining positions of the central and fringe maxima and their intensity ratios. Strains in oxidized samples are shown to be negative at the bottom surface and positive at the top surface of nanowires changing with depth in a concave way. The magnitudes of the strains at the bottom surface and at the top surface increase monotonically with increasing the oxidation time. The determined strain of a sample oxidized at 850 °C for 5 h is 0.50% at the top surface and −0.11% at the bottom surface.

Clarification of Additional Mobility Components associated with TaC and TiN Metal Gates in scaled HfSiON MOSFETs down to sub-1.0nm EOT

To clarify mobility (mu) limiting factors in aggressively scaled metal gate (MG)/high-k insulator (HK) MOSFETs, additional mu components associated with TaC and TiN MGs and their physical origins are investigated. With a TaC/HfSiON stack, mu@Eeff=1M V/cm of 215 cm2/Vs, 87% of Poly Si/SiO2 universal, at EOT of 0.91nm is achieved. Two different types of additional scattering are, for the first time, identified; the one is remote Coulomb scattering (RCS) by the charges near the HK-IL interface, induced by diffused metals, and the other becomes obvious near sub-1.0 nm-EOT region, plausibly originating from defects near the MG-HK interface.

A pure-CMOS nonvolatile multi-context configuration memory for dynamically reconfigurable FPGAs

Multi-context configuration memory stores multiple sets of configuration data and changes the entire configuration of FPGA quickly, enabling enhancement of hardware utilization with dynamic reconfiguration architectures. The memory area for one set of configuration data should be much smaller than the computational resource it controls. In this paper, we propose a pure-CMOS, nonvolatile, and small-footprint multi-context configuration memory. The multi-context memory includes multiple 2Tr nonvolatile memory elements, which are programmed by channel hot-electron injection, and allows context switching in a single clock cycle. A primitive dynamically reconfigurable device having a lookup table and minimum interconnect backed by 16-bit 8-context configuration memory was fabricated by a 0.18 um CMOS process and its functionality was demonstrated. The 2Tr nonvolatile memory element is more than 4 times denser than 6Tr SRAM, enabling achievement of greater logic density. The pure-CMOS and nonvolatile features would enhance the attractiveness of the technology in many applications.