Yuuki Tanaka

Efficient signed-digit-to-canonical-signed-digit recoding circuits

In this study, we propose a new signed-digit-to-canonical-signed-digit recoding circuit based on parallel prefix structures. Several articles have been devoted to the study of canonical signed-digit recoding circuits. However, most of those re-code from 2s complement binary number representation. Unlike those, our proposed architectures convert from signed-digit number representation. The circuit structure is somewhat different from those in previous articles, because each digit in the input is accompanied by its sign. We evaluate the proposed circuit and compare it with a circuit based on the conditional sum structure. We show that the proposed architectures performs faster by 30% or more than the circuit based on the conditional sum structure.

On the pagenumber of trivalent Cayley graphs

Book embedding of graphs is one of the graph layout problem. It is useful for the multiprocessor network layout or the fault-tolerant processor arrays. We show that the trivalent Cayley graphs proposed by Vadapalli and Srimani can be embedded in five pages, and show some additional results on cube-connected cycles.

A Minimum Feedback Vertex Set in the Trivalent Cayley Graph

In this paper, we study the feedback vertex set problem for trivalent Cayley graphs, and construct a minimum feedback vertex set in trivalent Cayley graphs using the result on cube-connected cycles and the Cayley graph representation of trivalent Cayley graphs.

An efficient diminished-1 modulo 2n + 1 multiplier using signed-digit number representation

In this paper, we propose a new modulo 2n + 1 multiplier for the diminished-1 representation. Our algorithm generates [n/4] +1 Signed-Digit(SD) numbers of n digits as the partial products and sums up these numbers by a multi-operand modulo 2n +1 SD adder. We found that the proposed multiplier is smaller and faster than several proposed circuits.

Efficient squaring circuit using canonical signed-digit number representation

Squaring and exponentiation of a number are fundamental arithmetic and widely used in the real-time applications such as image processing, digital filtering and cryptography. In this paper, we propose a squaring algorithm of an integer with canonical signed-digit (CSD) number representation. For an n-digit CSD number, our method generates n/4 CSD numbers of 2n-digit length as partial products. This result is half with respect to the conventional squaring algorithms. We implement the squaring circuit based on this algorithm and compare with some existing circuits. Our circuit is 40% faster than the known squaring circuit for binary numbers.

Recoding algorithms for minimal signed-digit numbers in residue number system

In this paper, new algorithms for obtaining minimal radix-two signed-digit (SD) representations in a residue number system (RNS) are proposed. At first, we present a recoding algorithm to convert an arbitrary p-digit SD number representation to the (p+1)-digit minimal SD representation, in which there are a fewest number of nonzero digits. The recoding method can be used for the number conversion from a p-digit SD number to a minimal p-digit SD number representation in an RNS. Then we propose the recoding algorithms for some kinds of moduli. By giving randomly SD numbers with 64 and 128 digits, the nonzero digits are reduced in a deletion rate of 33%. We also implement the efficient converters for special moduli based on the proposed algorithms.

Broadcasting Multiple Messages Using Cycle-Rooted Trees

In information dissemination problem on interconnection networks, problems of broadcasting and gossiping have been widely studied. In this paper, we study the other problem, called multi-source broadcasting, defined as follows: there are some (but not all) vertices each of which has the unique item of information and needs to disseminate to every other vertex. This problem is located at an intermediate position between broadcasting and gossiping. We analyze the multi-source broadcasting problem on the cycle-rooted tree and the de Bruijn digraph as an interconnection network.

A note on thek-degree Cayley graph

The k-degree Cayley graph is proposed by S.-Y. Hsieh and T.-T. Hsiao[1]. They have shown that the k-degree Cayley graph is a Cayley graph. However, definition and the proof in [1] are unsatisfactory and, indeed, untrue. Fortunately, that fact is not an evidence that k-degree Cayley graph is not a Cayley graph. In this paper, we show that k-degree Cayley graphs form a class of Cayley graphs by showing the Cayley graph obtained from some explicit group is isomorphic to the k-degree Cayley graph.

Dihedral Butterfly Digraph and Its Cayley Graph Representation

In this paper, we present a new extension of the butterfly digraph, which is known as one of the topologies used for interconnection networks. The butterfly digraph was previously generalized from binary to d-ary. We define a new digraph by adding a signed label to each vertex of the d-ary butterfly digraph. We call this digraph the dihedral butterfly digraph and study its properties. Furthermore, we show that this digraph can be represented as a Cayley graph. It is well known that a butterfly digraph can be represented as a Cayley graph on the wreath product of two cyclic groups [1]. We prove that a dihedral butterfly digraph can be represented as a Cayley graph in two ways.

Isomorphic factorization, the Kronecker product and the line digraph

In this paper, we investigate isomorphic factorizations of the Kronecker product graphs. Using these relations, it is shown that (1) the Kronecker product of the d-out-regular digraph and the complete symmetric digraph is factorized into the line digraph, (2) the Kronecker product of the Kautz digraph and the de Bruijn digraph is factorized into the Kautz digraph, (3) the Kronecker product of binary generalized de Bruijn digraphs is factorized into the binary generalized de Bruijn digraph.