Yuvraj Singh Dhillon

Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level

This paper proposes an optimum methodology forassigning supply and threshold voltages to modules in a CMOScircuit such that the overall energy consumption is minimizedfor a given delay constraint. The modules of the circuit shouldhave large enough gate depths such that the delay and energypenalties of the level shifters connecting them are negligible.Both static and dynamic energy are considered in theoptimization. Energy savings of up to 48% have been achievedon various example circuits. The first step in the optimizationfinds optimum supply and threshold voltages for each modulein the circuit. If the circuit has a large number of modules, thisstep might yield a correspondingly large number of differentsupply and threshold voltages for minimum energyconsumption. Since having a large number of different supplyand threshold voltages on an IC is not feasible in currenttechnologies, an additional step clusters the multiple voltagesobtained from the first step into a fixed number of supply andthreshold voltages (for example, 2 different supply voltagesand 2 different threshold voltages). In addition to theapplication of this method to circuit optimization, it can also beapplied to a wide range of problems with delay constraints,such as software tasks running on a dynamically variable V{DD}and V{th} processor.

Design of adaptive nanometer digital systems for effective control of soft error tolerance

Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are the reduced node capacitances and noise margins caused by feature size and supply voltage scaling. Static soft error optimization (such as concurrent error detection or gate resizing) can be very expensive in terms of power consumption if the circuit is not always exposed to high flux of particles. This paper proposes a scheme for dynamic control of soft error tolerance in digital circuits that has negligible power and delay overhead when the circuit is in its normal mode of operation. The key objective is to design circuits that can adapt to different radiation conditions with minimal power overhead. The soft error rate of the circuit is monitored by simple on-chip circuitry, and circuit soft error tolerance is controlled by using dynamic supply voltage and threshold voltage modulation together with variable capacitance banks.

Sizing CMOS circuits for increased transient error tolerance

The continuous shrinking of microelectronic device sizes with every technology generation, along with the reduction in supply voltages, is causing a significant decrease in circuit noise margins. This leads to increased susceptibility of circuits to transient errors. In this paper, we propose a methodology to increase the robustness of combinational circuits to transient errors by sizing the gates of the circuit in such a way that the number of errors propagated to the primary output is minimized while the timing requirement is met. Using SPICE simulation, we validate that combinational circuits propagate fewer numbers of transient errors to the circuit output after application of our sizing algorithm.

An O(N) supply voltage assignment algorithm for low-energy serially connected CMOS modules and a heuristic extension to acyclic data flow graphs

In this paper, a novel algorithm is proposed for assigning supply voltages to serially executing functional units (FUs) in a digital system such that the overall dynamic energy consumption is minimized for a given timing constraint. Novel closed form expressions for optimum supply voltage values are presented. The computation time of the algorithm is O(N) for N FUs in series. An extension of the O(N) algorithm is proposed for optimizing the acyclic data flow graph associated with any given task. Given the number of FUs available for the task, the operations required for the task are scheduled on the FUs. Voltages are then assigned to the FUs on each path of the flow graph using the O(N) algorithm. Energy savings of 10-60% are achieved on DSP filter designs using the proposed high-level optimization methodology over single supply voltage designs.

Power-performance trade-offs in second level memory used by an ARM-like RISC architecture

Power consumption is an important dimension in microprocessor and digital system design. This is especially true in the embedded setting where microprocessors have to operate without the luxury of a large power supply or cooling structures. In this paper, we describe an infrastructure setup for the study of power-performance tradeoffs in microprocessor architecture and compiler optimizations. This infrastructure distinguishes itself from those already proposed in the literature in its use of power estimations based on synthesis of the architecture and the full integration of a well-established optimizing compiler framework. We present some preliminary results where we show how the circuit level and architectural techniques can be combined to save overall system power. In particular we reduce the clock frequency and supply voltage of level two memory accesses (circuit level technique) and compensate for the resulting increase in the completion time by implementing a non-blocking store buffer (architectural technique) resulting in up to 39 % less power and up to 28 % less energy on a set of candidate benchmarks.