Yves Audet

A 1-V CMOS Current Reference With Temperature and Process Compensation

A 1-V current reference fabricated in a standard CMOS process is described. Temperature compensation is achieved from a bandgap reference core using a transimpedance amplifier in order to generate an intermediate voltage reference, VREF. This voltage applied to the gate of a carefully sized nMOS output transistor provides a reference drain current, IREF , nearly independent of temperature by mutual compensation of mobility and threshold voltage variations. The circuit topology allows for compensation of threshold voltage variation due to process parameters as well. The current reference has been fabricated in a standard 0.18-mum CMOS process. Results from nineteen samples measured over a temperature range of 0degC to 100degC , showed values of IREF of 144.3 muA plusmn 7% and VREF of 610.9 mV plusmn 2% due to the combined effect of temperature and process variations.

Design of a self-correcting active pixel sensor

Digital cameras are growing ever larger in silicon area and pixel count, which increases the occurrence of defects at fabrication time, or dead pixels that develop over their lifetime. An active pixel sensor self-correcting for most common faults is created by splitting the photodiode and readout transistors into two parallel portions with only a small area cost. Simulations show operation is the same for a single large device with no faults. When one half of the redundant pixel is stuck at low, output over a wide current range is reduced by 1.98 to 2.01. For one half stuck at high, faults output, after offset removal, is reduced by a factor of 1.85 to 1.92. Hence self-correction of the pixel can be performed with good accuracy via a simple shift circuit and with high accuracy with digital processing. Variation in transistor threshold voltages between the pixel halves of even 10% only causes modification of factors by 2-4%, hence giving a small effect.

Creating 35 mm camera active pixel sensors

A 36/spl times/24 mm active pixel sensor imaging area device is studied which would be ideal for use with standard 35 mm cameras. By applying multichip methods to active pixel sensors, the 39/spl times/30 mm system contains on board all the control circuitry and A/D converters, so the system outputs digital data. The large area requires a redundancy of design for a high yield. This starts with the active pixel cell, which able to withstand several defects and still be repairable, which CCD cells are not. The whole system is targeted at preventing bad rows or columns. By using spares in the row and column circuitry, as well as spare A/D converters the chip yield is only limited by a relatively small logic and control block. With repairs the yield of this 11.7 sq. cm system goes from almost nil to more than 80%-93% with modest defect densities of 1.5 to 0.5 per sq. cm. By being a retrofit for current 35 mm cameras, and having larger photodiode pixels than current APSs this CMOS device would be nearly as sensitive as CCDs but at much lower production costs and much higher yields.

A wide dynamic range CMOS digital pixel sensor

A CMOS image sensor with pixel level analog to digital conversion is presented. Each 13.8/spl mu/m /spl times/ 13.8/spl mu/m pixel area contains a photodiode and a dynamic comparator using the maximum voltage swing available (0V-1.8V). The comparator does not need any bias current and is insensitive to fabrication process variations. Also a digital to analog converter (DAC) is used to deliver a voltage reference in order to compare it with the pixel voltage for the analog to digital conversion. This DAC provides the possibility to convert the pixel voltage linearly or to compress it logarithmically. The circuit allows image captures at multiple exposure times, and the resulting values are delivered in floating digital format, offering the possibility to expand the intrascene dynamic range to more than 84 dB. The circuit was implemented in a CMOS 0.18/spl mu/m process and has been submitted for fabrication.

A self-correcting active pixel sensor using hardware and software correction

Active pixel sensor (APS) CMOS technology reduces the cost and power consumption of digital imaging applications. We present a highly reliable system for the production of high-quality images in harsh environments. The system is based on a fault-tolerant architecture that effectively combines hardware redundancy in the APS cells and software correction techniques.

A multiple operation mode CMOS digital pixel sensor dedicated to a visual cortical implant

A CMOS image sensor with pixel level analog to digital conversion is presented. The circuit of each pixel contains a photodiode, with a fill factor of 21%, a shutter/follower, a comparator and a storing unit, for a total of 44 transistors. The comparator uses the maximum voltage swing available and is insensitive to fabrication process variations. A digital to analog converter is used to deliver a voltage reference in order to compare it with the pixel voltage for the analog to digital conversion. The digital value of the pixel voltage is stored in an 8-bit DRAM. The circuit can operate in one of the three following modes: logarithmic, linear integration or differential. The first two modes are used for image capture and the third mode is used for an active range finder system. All these modes are required by a visual cortical implant. The circuit layout of a pixel is being fabricated in CMOS 0.18 /spl mu/m technology, and a matrix of 45/spl times/90 pixels was submitted for fabrication.

Implementation and testing of fault-tolerant photodiode-based active pixel sensor (APS)

The implementation of imaging arrays for system-on-a-chip (SOC) is aided by using fault-tolerant light sensors. Fault-tolerant redundancy in an active pixel sensor (APS) is obtained by splitting the photodiode and readout transistors into two parallel operating devices, while keeping a common row select transistor. This creates a redundant APS that is self-correcting for most common faults. Simulations suggest that, by combining hardware fault-tolerance capability with software correction, active pixel sensor arrays could be virtually immune to defects. To test this concept in hardware, a fault-tolerant photodiode APS was designed and fabricated using a CMOS 0.18 /spl mu/m process. Testing included both fully functional APS, and those in which various failure modes and mechanisms are introduced (equivalent to stuck low and stuck high faults). Test results show that the output voltage for the stuck high case and the stuck low case varies linearly with light intensity. For the stuck low case, the sensitivity is 0.57 of that for a non-defective redundant APS, and the stuck high case is 0.40. These deviate from the theoretical value of 0.5 by +14% and -20% respectively.

On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations

This paper presents a new experimental setup (to our knowledge, the first ever) and results obtained with that setup from which we report extra combinational delays in an SRAM FPGA (Virtex-5) due to transient ionizing radiations. The results, obtained by proton irradiation at the TRIUMF laboratory, show that our setup can detect extra combinatorial delays as small as 40 ps, and that delays of more than 400 ps can affect the targeted FPGA. These results strongly suggest that delay faults can potentially be induced by transient ionizing radiations.

Characteristics of fault-tolerant photodiode and photogate active pixel sensor (APS)

A fault-tolerant APS has been designed by splitting the APS pixel into two halves operating in parallel, where the photo sensing element has been divided in two and the readout transistors have been duplicated while maintaining a common row select transistor. This split design allows for a self correcting pixel scheme such that if one half of the pixel is faulty, the other half can be used to recover the entire output signal. The fault tolerant APS design has been implemented in a 0.18 /spl mu/m CMOS process for both a photodiode based and photogate based APS. Test results show that the fault tolerant pixels behave as expected where a non-faulty pixel behaves normally, and a half faulty pixel, where one half is either stuck low or high, produces roughly half the sensitivity. Preliminary results indicate that the sensitivity of a redundant pixel is approximately three times that of a traditional pixel for the photodiode APS and approximately twice that for the photogate APS.

On extra delays affecting I/O blocks of an SRAM-based FPGA due to ionizing radiation

This paper aims at characterizing additional delays induced by ionizing radiation in Input/Output Blocks (IOBs) of Static Random-Access Memory Based Field Programmable Gate Arrays (SRAM-Based FPGAs), using measurement techniques based on ring oscillators (ROs). This characterization effort includes experiments performed with proton irradiation at TRIUMF on Xilinx devices (Virtex-5 and Artix-7). Results from these irradiation experiments show that RO period variations, up to 6.2 ns for Virtex-5 and 3.8 ns for Artix-7, could be induced. These results also reveal that the occurrence rate of events (namely delays and breaks) affecting ROs implemented in IOBs is approaching the rate observed when ROs are implemented in the FPGA core, even if the number of configuration bits dedicated to IOBs is significantly lower than for the FPGA core. These radiation test experiments are supported by emulation using similar RO-based measurement techniques and Xilinx SEU Controller as a fault injector. The fault injection experiments allow a better understanding of the behaviour of IOBs affected by additional delays due to configuration bit flips, which in many cases is similar to what can be observed with an incorrect parameter setting. Emulation experiments also reveal that many of the events modifying IOB behaviour are found to require multiple bit fault injection.