Z.C. Yang

Electrical coupling suppression and transient response improvement for a microgyroscope using ascending frequency drive with a 2-DOF PID controller

In this paper, we demonstrate a novel control strategy for the drive mode of a microgyroscope using ascending frequency drive (AFD) with an AGC-2DOF PID controller, which drives a resonator with a modulation signal not at the resonant frequency and senses the vibration signal at the resonant frequency, thus realizing the isolation between the actual mechanical response and electrical coupling signal. This approach holds the following three advantages: (1) it employs the AFD signal instead of the resonant frequency drive signal to excite the gyroscope in the drive direction, suppressing the electrical coupling from the drive electrode to the sense electrode; (2) it can reduce the noise at low frequency and resonant frequency by shifting flicker noise to the high-frequency part; (3) it can effectively improve the performance of the transient response of the closed-loop control with a 2-DOF (degree of freedom) PID controller compared with the conventional 1-DOF PID. The stability condition of the whole loop is investigated by utilizing the averaging and linearization method. The control approach is applied to drive a lateral tuning fork microgyroscope. Test results show good agreement with the theoretical and simulation results. The non-ideal electrical antiresonance peak is removed and the resonant peak height increases by approximately 10 dB over a 400 Hz span with a flicker noise reduction of 30 dB within 100 Hz using AFD. The percent overshoot is reduced from 36.2% (1DOF PID) to 8.95% (2DOF PID, about 75.3% overshoot suppression) with 15.3% improvement in setting time.

Electrical coupling suppressing for a microgyroscope using ascending frequency drive with 2-DOF PID controller

This work demonstrates a novel control strategy for the drive mode of a MEMS gyroscope using ascending frequency drive with AGC-2DOF PID controller instead of resonant frequency drive. It can suppress the electrical coupling from the drive electrodes to the sense electrodes, reduce the low frequency noise and improve the transient response by using 2DOF PID controller. Test results indicate the electrical antiresonance peak is eliminated and the resonant peak height increases approximate 10dB over 400Hz span with a flicker noise reduction of 30dB within 100Hz. The percent overshoot is reduced from 36.2% (1DOF PID) to 8.95% (2DOF PID) with 15.3% improved in setting time. The scale factor is measured to be 5.6mv/deg/s with nonlinearity about 0.95% in the full range of 800deg/s.

A doubly decoupled micromachined vibrating wheel gyroscope

In this paper, a doubly decoupled vibrating wheel gyroscope with novel torsional sensing comb capacitors is presented. The doubly decoupled design and symmetrical structure can efficiently suppress the mechanical coupling of the gyroscope. Moreover, the symmetrically distributed proof masses make it immune from the linear accelerations. Both driving and sensing modes of the gyroscope are dominated by slide film air damping, so it can work even at atmospheric environment. The process for this gyroscope is also compatible with z-axis gyroscope, which makes it potential to realize low cost monolithic MIMU (miniature inertial measurement unit) without vacuum packaging. The gyroscope was fabricated and tested at atmosphere. The sensitivity is 3.1mV/º/s while the nonlinearity is 7.68‰ with the full scale of 900º/s. The noise floor is 0.45º/s/Hz1/2.

Design of a digital closed control loop for the sense mode of a mode-matching MEMS vibratory gyroscope

This paper presents a digital closed loop control method for the sense mode of a mode-matching MEMS vibratory gyroscope. The sense closed loop system reported in our previous work is relatively complex and unreliable due to the existence of notch filter. In this work, a more simple and robust control system is realized with the help of mode-matching control. With a tuning voltage automatically applied on the tuning combs of the gyroscope, a frequency split of less than 0.3 Hz is achieved. Experimental results show that the mode-matched gyroscope achieves a scale factor of 18.5mV/deg/s with a nonlinearity of 0.088% and a bias instability of 2.7deg/h.

A vision chip architecture for image recognition based on improved convolutional neural network

In this paper, we propose a novel architecture of vision chip based on CNN (convolutional neural network) and improve the traditional LeNet-S algorithm. From the results of the experiment and performance, the accuracy of the proposed chip with LeNet-S increased to 97.29%. According to the characteristic of deep pipeline among independent layers of CNN, a 3-stage pipeline CCE (Convolutional Computing Element) is designed and also introduce the logical data flow in CCE array in detail. Finally the data compression and decompression circuit are added to the vision system to reduce the bandwidth of off-chip memory which is the highest cost in data transmission. The storage reduction is nearly to 30%, depending on the image processed.

A high-G acceleration latching switch with integrated normally-open/close paths independent to the proof-mass

An acceleration latching switch with integrated normally Open/Close paths is presented in this paper. Two arch trusses used as fracture parts of the normally-close path are connected in series to form the normally close path, which will be broken and latched by the latching mechanism to reach the open state once the input acceleration beyond threshold. Moreover, the normally-open path is consisted of multi-contact and both paths are mechanically separated from the proof mass to prevent them from the impact resulted from the vibration of the proof mass at the latched state. The switch was fabricated by a two-mask silicon-on-glass process and tested. The latching shock is 1 5000G and the response time is about 0.1ms. The normally-close path has a resistance of 4Ω and a maximum current of 100mA while the normally-open path has a contact resistance of no more than 3.7Ω and the safe applied current is up to 140mA.

Evaluation of ultra-low power Tunneling Field Effect Transistor power management unit

In this paper, we propose a TFET (Tunneling Field Effect Transistor) PMU (power management unit) of R80515 for ultra-low power. Both the dynamic power and leakage power are evaluated by HSPICE circuit simulation with Verilog-A models. From the simulation, we find the dynamic power of TFET circuits can be reduced by 80% and leakage power reduction can be nearly 30% compared with 130nm CMOS (Complementary Metal Oxide Semiconductor) implementation. The results indicate that TFET can achieve much higher power efficiency and the replacement can be vital to the whole design.

The design and implementation of a reconfigurable convolution operator based on APU

In order to achieve fast IC design, reduce development cycle and cost, Key Lab of Integrated Microsystems in Peking University proposed Array Processing for Unification Architecture(APU) which consists of four kinds of operators: computation, data path, control and MEM operators to replace the configurable logic block in current FPGA fabric. In this paper, a reconfigurable convolution operator based on APU, is presented which is used to convolutional neural network computing. The reconfigurable convolution operator is with more coarse-grain and function changeable than APU. And the process of operator synthesis is verified by simulation-based verification and formal verification separately. With the verification method proposed in this paper, certainty and completeness have been achieved. The results show that compared with the hardware design at the cost of resources based APU, this methodology can obtain hardware of suitable performance with regular structure with the cost of 34.08% less area and 25.26% lower power.

The implementation of CRC-16 based on a novel FPGA: A collection of reconfiguration operations(ReOps)

This paper presents the implementation of CRC-16 on a novel FPGA, a collection of reconfigurable operators (ReOps), which has smaller configuration bits-stream and better performance than traditional FPGA. A ReOp is a basic block which can process multiple bits data with a specific function set. Considering the complete function set of ReOps, we divide ReOps into eight groups: Arithmetic ReOps, Multiplier ReOps, Bit-wise logic ReOps, Shift ReOps, Multiplexer ReOps, Memory ReOps, Register ReOps, Multiplexer ReOps, Control ReOps. The function collection of ReOps is soundness for the arbitrary ASIC(Application Special Integrated Circuit). We implement the CRC-16 on this novel FPGA, the experimental results show that compared with the traditional FPGA, this novel FPGA has advantages in delay and configuration bits-stream.

The implementation of a KNN classifier on FPGA with a parallel and pipelined architecture based on Predetermined Range Search

K-nearest neighbor (KNN) classification algorithm performs slowly for large scale training set and high dimensions. To overcome the disadvantage, we need to focus on the points within a predetermined range, without changing the precision. This method is named Predetermined Range Search (PRS). In this paper, we proposed a method to find the reference distance (ReDist), a parallel and pipelined architecture based on PRS to implement KNN classification algorithm on FPGA. Besides, we use real SPECT dataset for evaluation. The result shows that clock frequency is up to 186.4MHz on Virtex 4 which is 1.4× faster than the conventional design. Meanwhile, this novel architecture has a smaller BRAMs (Block RAMs) coverage and a simpler circuit structure.