Z.J. Shen

New Physical Insights on Power MOSFET Switching Losses

Realistic estimation of power MOSFET switching losses is critical for predicting the maximum junction temperature and efficiency of power electronics circuits. The purpose of this paper is to investigate the internal physics of MOSFET switching processes using a physically based semiconductor device modeling approach, and subsequently examine the commonly used power loss calculation method in light of the new physical insights. The widely accepted output capacitance loss term is found to be redundant and erroneous based on the new modeling and measurement results. In addition, the existing method of approximating switching times with the power MOSFET gate charge parameters grossly overestimates the switching power loss. This paper recommends a new MOSFET gate charge parameter specification and an effective switching time estimation method to compensate for the power loss calculation error introduced by the two-slope voltage transition waveform of the power MOSFET.

Power MOSFET Switching Loss Analysis: A New Insight

Realistic estimation of power MOSFET switching losses is critical for predicting the maximum junction temperature and efficiency of power electronics circuits. The purpose of this paper is to investigate the internal physics of MOSFET switching processes using a physically based semiconductor device modeling approach, and subsequently examine the commonly used power loss calculation method based on the new physical insights. The widely accepted output capacitance loss term in this calculation method is found to be redundant and erroneous. In addition, the current method of approximating switching times with power MOSFET gate charge parameters grossly overestimates the switching power loss. This paper recommends a new MOSFET gate charge parameter specification and an effective switching time estimation method to compensate for the power loss calculation error introduced by the two slope voltage transition waveform of the power MOSFET

Design Considerations for Maintaining DC-Side Voltage of Hybrid Active Power Filter With Injection Circuit

Hybrid active power filter with injection circuit (IHAPF) shows great promise in reducing harmonics and improving power factor with a relatively low capacity active power filter, but suffers from DC-side voltage instability that inadvertently impacts the compensation performance and safety of the IHAPF. In this paper, two new methods are proposed to overcome this major technical challenge with a hysteretic control and energy release circuit, and a controllable pulsewidth modulation (PWM) rectifier. Modeling, theoretical analysis, and experimental results have verified that both methods can stabilize DC-side voltage within a certain range. A prototype IHAPF system was built incorporating the PWM rectifier DC voltage control scheme, and installed in a 220 kV substation in Southern China. It demonstrated significant improvement in harmonics reduction and power factor. The DC voltage stability issue was also resolved with the new design.

Lateral power MOSFET for megahertz-frequency, high-density DC/DC converters

DC/DC converters to power future CPU cores mandate low-voltage power metal-oxide semiconductor field-effect transistors (MOSFETs) with ultra low on-resistance and gate charge. Conventional vertical trench MOSFETs cannot meet the challenge. In this paper, we introduce an alternative device solution, the large-area lateral power MOSFET with a unique metal interconnect scheme and a chip-scale package. We have designed and fabricated a family of lateral power MOSFETs including a sub-10 V class power MOSFET with a record-low R/sub DS(ON)/ of 1m/spl Omega/ at a gate voltage of 6V, approximately 50% of the lowest R/sub DS(ON)/ previously reported. The new device has a total gate charge Q/sub g/ of 22nC at 4.5V and a performance figures of merit of less than 30m/spl Omega/-nC, a 3/spl times/ improvement over the state of the art trench MOSFETs. This new MOSFET was used in a 100-W dc/dc converter as the synchronous rectifiers to achieve a 3.5-MHz pulse-width modulation switching frequency, 97%-99% efficiency, and a power density of 970W/in/sup 3/. The new lateral MOSEFT technology offers a viable solution for the next-generation, multimegahertz, high-density dc/dc converters for future CPU cores and many other high-performance power management applications.

Integration of a Monolithic Buck Converter Power IC and Bondwire Inductors With Ferrite Epoxy Glob Cores

In this letter, we report a concept of integrating a monolithic buck converter power IC with in-package bondwire inductors. The power IC containing all switching devices, driver circuitry, and control logic was designed and fabricated with a standard 0.5-μm CMOS process. Mutliturn bondwires with and without ferrite epoxy glob cores are used as the filter inductor in the buck converter. A prototype system-in-package converter with an output voltage and current of 2.5 V and 120 mA was built to operate at frequencies up to 5 MHz. The power level of the prototype buck converter is scalable by increasing the size of the active power switches.

A Prognostic and Warning System for Power Electronic Modules in Electric, Hybrid, and Fuel Cell Vehicles

Reliability of power electronics modules is of paramount importance for the commercial success of various types of electric vehicles. In this paper, we study the technical feasibility of detecting early symptoms and warning signs of power module degradation due to thermomechanical stress and fatigue, and developing a prognostic system that monitors the state of health of the power modules in electric, hybrid, and fuel cell vehicles. A signature degradation trace of the on-voltage of IGBT modules was observed from accelerated power cycling test. This on-voltage anomaly can be attributed to sequential events of solder joint degradation followed by wirebond lift-off mechanisms. A quasi real-time IGBT failure prognostic algorithm based on monitoring the abnormal VCEsat variation at specific currents and temperatures is developed. The algorithm was verified using extensive SIMULINK modeling. The prognostic system can be implemented cost-effectively in existing vehicle hardware/software architectures

On-chip bondwire transformers for power SOC applications

In this paper, a novel concept of on-chip bondwire transformer with ferrite epoxy glob is proposed for power system on chip (SOC) applications. We have theoretically and experimentally proven the concept of the bondwire transformer and demonstrated that its performance can be improved using ferrite polymer epoxy glob. Transformer parameters including self- and mutual inductance, and coupling factors are extracted from both modeled and measured S-parameters. It is expected that the bondwire transformers can be easily integrated into power SOC manufacturing processes with minimal changes in processes, and open enormous possibilities for realizing cost- effective, high current, high efficiency power SOCs.

A Dynamic Hybrid Var Compensator and a Two-Level Collaborative Optimization Compensation Method

In this paper, a dynamic hybrid var compensator (HVC) for distribution grid is proposed. The system is based on a combination of a small-capacity distribution static compensator (DSTATCOM) and multigroup large-capacity thyristor switched capacitor (TSC). The DSTATCOM is the continuous subsystem of HVC, and the TSCs are the discrete subsystem of HVC. A new hybrid control method based on expert decision has been proposed to make sure that the HVC has good performance. A two-level collaborative optimization arithmetic, which is used to decide the optimal capacity of each HVC, has been proposed in this paper. A dynamic energy-saving system based on HVCs has been developed for a melt factory in southern China; application results show that compared to traditional reactive power compensation systems, the proposed system can effectively correct power factor, support supply voltage, mitigate voltage flicker, and obtain good effect for energy saving with low cost.

On-Chip Bondwire Inductor with Ferrite-Epoxy Coating: A Cost-Effective Approach to Realize Power Systems on Chip

A novel concept of on-chip bondwire inductors with ferrite epoxy coating is proposed to provide a cost effective approach realizing power systems on chip (SOC). A Q factor of 30-40 is experimentally demonstrated which represents an improvement by a factor of 3-30 over the state-of-the-art MEMS micromachined inductors. More importantly, the bondwire inductors can be easily integrated into power SOC manufacturing processes with minimal changes, and open enormous possibilities for realizing cost-effective, high current, high efficiency power SOCs.

Lateral discrete power MOSFET: enabling technology for next-generation, MHz- frequency, high-density DC/DC converters

DC/DC converters to power future CPU or DSP cores mandate low-voltage power MOSFETs with ultra low on-resistance and gate charge. Conventional trench MOSFETs cannot meet the challenge. We introduce an alternative device technology, the discrete lateral power MOSFETs, to overcome the limitations associated with the vertical trench or planar MOSFETs. We report a family of 7V, 20V, and 30V lateral discrete power MOSFETs with figures of merit 2-3 times better than the state-of-the-art trench MOSFETs. We have developed an innovative metal interconnect and chip-scale packaging approach to overcome the scaling barrier which limits the chip size and current rating of the traditional lateral power devices. The lateral MOSFETs were designed and fabricated with a simplified CMOS process, and packaged in flip-chip forms using a wafer bumping technology. Lateral discrete power MOSFETs will become a viable enabling technology for next-generation, MHz-frequency, high-density DC/DC converters.