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Dive into the research topics where Zaher S. Andraus is active.

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Featured researches published by Zaher S. Andraus.


theory and applications of satisfiability testing | 2005

A branch-and-bound algorithm for extracting smallest minimal unsatisfiable formulas

Maher N. Mneimneh; Inês Lynce; Zaher S. Andraus; Joao Marques-Silva; Karem A. Sakallah

We tackle the problem of finding a smallest-cardinality MUS (SMUS) of a given formula. The SMUS provides a succinct explanation of infeasibility and is valuable for applications that rely on such explanations. We present a branch-and-bound algorithm that utilizes iterative MAXSAT solutions to generate lower and upper bounds on the size of the SMUS, and branch on specific subformulas to find it. We report experimental results on formulas from DIMACS and DaimlerChrysler product configuration suites.


design automation conference | 2004

Automatic abstraction and verification of verilog models

Zaher S. Andraus; Karem A. Sakallah

Abstraction plays a critical role in verifying complex sys-tems. A number of languages have been proposed to model hardware systems by, primarily, abstracting away their wide datapaths while keeping the low-level details of their control logic. This leads to a significant reduction in the size of the state space and makes it possible to verify intricate control interactions formally. These languages, however, require that the abstraction be done manually, a tedious and error-prone process. In this paper we describe Vapor, a tool that auto-matically abstracts behavioral RTL Verilog to the CLU lan-guage used by the UCLID system. Vapor performs a sound abstraction with emphasis on minimizing false errors. Our method is fast, systematic, and complements UCLID by serving as a back-end for dealing with UCLID counterexamples. Preliminary results show the feasibility of automatic abstraction and its utility in formal verification.


asia and south pacific design automation conference | 2006

Refinement strategies for verification methods based on datapath abstraction

Zaher S. Andraus; Mark H. Liffiton; Karem A. Sakallah

In this paper, we explore the application of counter-example-guided abstraction refinement (CEGAR) in the context of microprocessor correspondence checking. The approach utilizes automatic datapath abstraction augmented with automatic refinement based on 1) localization, 2) generalization, and 3) minimal unsatisfiable subset (MUS) extraction. We introduce several refinement strategies and empirically evaluate their effectiveness on a set of microprocessor benchmarks. The data suggest that localization, generalization, and MUS extraction from both the abstract and concrete models are essential for effective verification. Additionally, refinement tends to converge faster when multiple MUses are extracted in each iteration.


Constraints - An International Journal | 2009

A branch and bound algorithm for extracting smallest minimal unsatisfiable subformulas

Mark H. Liffiton; Maher N. Mneimneh; Inês Lynce; Zaher S. Andraus; Joao Marques-Silva; Karem A. Sakallah

Explaining the causes of infeasibility of Boolean formulas has practical applications in numerous fields, such as artificial intelligence (repairing inconsistent knowledge bases), formal verification (abstraction refinement and unbounded model checking), and electronic design (diagnosing and correcting infeasibility). Minimal unsatisfiable subformulas (MUSes) provide useful insights into the causes of infeasibility. An unsatisfiable formula often has many MUSes. Based on the application domain, however, MUSes with specific properties might be of interest. In this paper, we tackle the problem of finding a smallest-cardinality MUS (SMUS) of a given formula. An SMUS provides a succinct explanation of infeasibility and is valuable for applications that are heavily affected by the size of the explanation. We present (1) a baseline algorithm for finding an SMUS, founded on earlier work for finding all MUSes, and (2) a new branch-and-bound algorithm called Digger that computes a strong lower bound on the size of an SMUS and splits the problem into more tractable subformulas in a recursive search tree. Using two benchmark suites, we experimentally compare Digger to the baseline algorithm and to an existing incomplete genetic algorithm approach. Digger is shown to be faster in nearly all cases. It is also able to solve far more instances within a given runtime limit than either of the other approaches.


design automation conference | 2004

AMUSE: a minimally-unsatisfiable subformula extractor

Yoonna Oh; Maher N. Mneimneh; Zaher S. Andraus; Karem A. Sakallah; Igor L. Markov


international conference on logic programming | 2008

Reveal: A Formal Verification Tool for Verilog Designs

Zaher S. Andraus; Mark H. Liffiton; Karem A. Sakallah


Archive | 2013

Automated scalable verification for hardware designs at the register transfer level

Zaher S. Andraus; Karem A. Sakallah; Mark H. Liffiton


Archive | 2009

Automatic formal verification of control logic in hardware designs

Karem A. Sakallah; Zaher S. Andraus


Unknown Journal | 2004

AMUSE: A minimally-unsatisfiable subformula extractor

Yoonna Oh; Maher N. Mneimneh; Zaher S. Andraus; Karem A. Sakallah; Igor L. Markov

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Yoonna Oh

University of Michigan

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Inês Lynce

Technical University of Lisbon

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