Zakariae Chbili

SOI Field-Effect Diode DRAM Cell: Design and Operation

A dynamic RAM cell based on the field-effect diode (FED) is presented, and its operation is described and explained with the help of numerical device simulations. This new cell resembles the thin capacitively coupled thyristor (TCCT) cell in concept and operation, however it has important advantages. These advantages derive from the fact that the thyristor-like mode of operation of the FED is gate induced, whereas the TCCT is an actual, built-in thyristor. High read 0/1 current margin, fast write/read time, good retention, and densely packed cells are obtained.

Time Dependent Dielectric Breakdown in High Quality SiC MOS Capacitors

In this paper we report TDDB results on SiO2/SiC MOS capacitors fabricated in a matured production environment. A key feature is the absence of early failure out of over 600 capacitors tested. The observed field accelerations and activation energies are higher than what is reported on SiO2/Si of similar oxide thickness. The great improvement in oxide reliability and the deviation from typical SiO2/SiC observations are explained by the quality of the oxide in this study.

SOI FED-SRAM Cell: Structure and Operation

A static memory cell (SRAM) based on the field-effect diode (FED) is presented, and its operation is explained with the help of numerical device simulations. Although this new cell resembles the thin-capacitively coupled-thyristor (TCCT) SRAM cell in concept and operation, it is nevertheless characterized by significant advantages. These advantages derive from the fact that the thyristorlike mode of operation of the FED is gate induced, whereas the TCCT is an actual built-in thyristor. The operation of the cell is explained with the help of suitable timing diagrams, and the mechanisms of storing 1 and 0 are analyzed with detailed numerical simulations. In one operation scheme (where the cell could better be termed quasi-SRAM), a sequence of restore pulses is periodically applied after the cell is put on Hold, which ensures that the stored data remain valid for as long as the cell is powered ON. High read 0/1 current margin, fast write/read time, and densely packed cells are among the cell advantages obtained.

Unusual bias temperature instability in SiC DMOSFET

We observe an unusual instability in the SiC DMOSFET transistor characteristics. From a series of bias conditions at elevated temperatures, we conclude that a high density of hole traps in the oxide near the SiO2/SiC interface are responsible.

Physics and design of a SOI Field-Effect-Diode memory cell

A new family of well behaved memory cells based on the SOIFED has been described and their operation explained. Their operation relies on modifying the conductivity of the SOI film locally by suitably biasing the gates. They are easier to fabricate and their performance is excellent.

Modeling Early Breakdown Failures of Gate Oxide in SiC Power MOSFETs

One of the most serious technology roadblocks for SiC DMOSFETs is the significant occurrence of early failures in time-dependent-dielectric-breakdown testing. Conventional screening methods have proved ineffective, because the remaining population is still plagued with poor reliability. The traditional local thinning model for extrinsic (early) failures, which guides the screening through burn-in measures, simply does not work. The fact that improved cleanliness control in the fabrication process does little to reduce early failures also suggests that local thinning due to contamination is not the root cause. In this paper, we propose a new lucky defect model where bulk defects in the gate oxide, introduced during growth, are responsible for the early failures. We argue that a local increase in leakage current via trap-assisted tunneling leads to early oxide breakdown. This argument is supported with oxide breakdown observations in SiC/SiO2 DMOSFETs, as well as simulations that examine various defect distributions and their impact on the resultant early failure distributions.

Design and analysis of multi-gate field-effect-diodes for embedded memory

Memory arrays consume a very large area in chip designs; yet memory cell scaling lags significantly transistor scaling. With transistor channel lengths in the nanoscale regime, the six transistor static random access memory cell (6T-SRAM) and the single transistor dynamic memory (DRAM) cell both suffer from excessive leakage current. Consequently, there is a widely recognized need for urgent progress in memory technology.

Self-heating impact on TDDB in bulk FinFET devices: Uniform vs Non-uniform Stress

Self-heating is a growing concern for thin-body devices. In this paper, we discuss the impact of self-heating on TDDB using uniform and non-uniform gate dielectric stress. We show lifetime reduction with increasing drain voltages consistent with elevated temperature stress. It is also shown that the power law dependence to gate voltage is preserved at different drain voltages. Due to limited self-heating during nominal device operation TDDB lifetime is not reduced for CMOS circuits.

Fast TDDB for early reliability monitoring

This work presents a new experimental setup to perform highly accelerated Time Dependent Dielectric Breakdown (TDDB) in constant voltage stress (CVS) mode with capability of collecting failure distributions in sub millisecond regime. The new apparatus is capable of collecting failure times down to tens of microseconds and we demonstrate that power law dependence with respect to gate voltage down to hundreds of microseconds is valid irrespective of technology. We argue that the implementation of fast TDDB setup for early reliability evaluation would complement the use of voltage ramped stress (VRS), shorten the time for learning cycles, and provide early guidance for reliability assessments.

Massively parallel TDDB testing: SiC power devices

This paper presents a novel experimental setup to perform wafer level TDDB testing. The massively parallel reliability system is capable of testing a total of 3000 probes simultaneously. The system can perform tests at temperatures up to 400 °C for high temperature applications (SiC). We also present TDDB results of SiO2 on SiC showing higher TDDB lifetime and field acceleration compared to SiO2 on Si.