A. Kerber

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

Understanding mobility mechanisms in extremely scaled HfO 2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and V t -tuning dipoles with gate-first process

We demonstrate a novel “remote interfacial layer (IL) scavenging” technique yielding a record-setting equivalent oxide thickness (EOT) of 0.42 nm using a HfO2-based MOSFET high-к gate dielectric. Intrinsic effects of IL scaling on carrier mobility are clarified using this method. We reveal that the mobility degradation observed for La-containing high-к is not due to the La dipole but due to the intrinsic IL scaling effect, whereas an Al dipole brings about additional mobility degradation. This unique nature of the La dipole enables aggressive EOT scaling in conjunction with IL scaling for the 16 nm technology node without extrinsic mobility degradation.

Fundamental aspects of HfO 2 -based high-k metal gate stack reliability and implications on t inv -scaling

Experimental reliability trends indicate that tinv-scaling with HKMG stacks remains challenging because NBTI, PBTI and TDDB reliability margins rapidly decrease with decreasing tinv values and increasing gate leakage current. A case is made that these observed trends arise from the layer structure and the materials properties of the SiO(N)/HfO2 dual dielectric. Therefore, fundamental reliability limitations appear to increasingly impact HKMG stack scaling.

Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies

Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and to discuss the impact of BTI recovery and wafer-to-wafer variation on the BTI statistics. We demonstrate a correlation between time-zero VT and ΔVT and illustrate the minor impact of BTI induced variability on post-stress VT distributions relevant for modeling the circuit aging.

Universality of NBTI - From devices to circuits and products

This paper showcases the universality of NBTI and its dependencies on time, bias, temperature, AC frequency and pulse duty cycle across different process integration schemes used in the industry and technology nodes. Strong correlation has been established between device, circuit, and product degradation. Different aspects of variability and variable NBTI in small area devices have been discussed. Features that are important from an industrial perspective are highlighted. Any NBTI model should address these aspects to be considered relevant.

PBTI relaxation dynamics after AC vs. DC stress in high-k/metal gate stacks

A detailed study on PBTI relaxation after AC and DC stress in high-k nFETs is reported. First, Vt shift during AC and DC stress are examined, showing that the PBTI time evolution depends on the stress mode due to the relaxation effect. Then, comparison of relaxation after different stress types reveals large difference in the relaxation behavior at short times, whereas AC and DC relaxation are observed to merge at longer times. The “time-to-merge” rapidly increases with stress time and it strongly depends on the duty cycle. From a series of “Stress-Relax-Stress” measurement, we also demonstrate that the charge trapping and de-trapping process are highly correlated through “trap level”. A simple model from a trap distribution point of view is proposed to rationalize the above observations. These observations provide new insight into the trapping dynamics during PBTI.

Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs

The root cause for the increase in the TDDB voltage acceleration with decreasing stress voltage in metal gate/high-k n-channel FETs is investigated. Using DC and AC stress methodologies, the effect could be linked to charge trapping in the high-k gate dielectric. Furthermore, a correction for charge trapping is proposed, which results in a single power law voltage dependence for all stress conditions.

Methodology for Determination of Process Induced BTI Variability in MG/HK CMOS Technologies Using a Novel Matrix Test Structure

Process variations in addition to random stochastic variations contribute to variability in aggressively scaled CMOS devices. To decouple the process variation from the random stochastic variations, a novel transistor test structure utilizing a matrix configuration is introduced. Based on this structure, it is shown that the local VT and local bias temperature instability (BTI)-induced variance scales inversely with the gate oxide area over a range of 1000x, whereas process variations lead to saturation in the variance when determined using samples across the wafer. The gate area dependence of the VT and the BTI-induced variance can be modeled independently using two stochastic processes.

Correlation of I d - and I g -random telegraph noise to positive bias temperature instability in scaled high-κ/metal gate n-type MOSFETs

Random telegraph noise (RTN) in high-κ nMOSFETs is directly linked to Positive Bias Temperature Instability (PBTI). For the first time, the correlation between I<inf>d</inf>- and I<inf>g</inf>-RTN is clearly observed in high-κ MOSFET. I<inf>g</inf>-RTN is directly related to physical trapping or de-trapping and the I<inf>d</inf>-RTN reflects sensitivity to charge trapping as determined by gm, which is confirmed by both experiments and TCAD simulations.

Bias temperature instability in High-κ/metal gate transistors - Gate stack scaling trends

With the introduction of High-k, metal gates and alternate substrates into the gate-stack at the 45nm and 32nm technology nodes, Bias Temperature Instability (BTI) phenomena have had to be included into the chip design modeling. In this paper, we explore BTI trends with High-k transistors in manufacturing ready CMOS processes with gate last and gate first type process flows. In both flows, Positive Bias Temperature Instability (PBTI) is a strong function of the interface and High-k thickness, with aggressive interface scaling having significant adverse reliability implications. Negative Bias Temperature Instability, on the other hand, is strongly dependent on the quality of the interface and its nitrogen content. The introduction of germanium into the Si channel is found to significantly improve NBTI. With recovery effects being strong in both NBTI and PBTI, AC BTI models in realistic circuit designs are critical to accurately evaluate the BTI lifetime of chips.