Zaven Kalayjian

Polarization imaging: principles and integrated polarimeters

Polarization is a general descriptor of light and contains information about reflecting objects that traditional intensity-based sensors ignore. Difficult computer vision tasks such as image segmentation and object orientation are made tractable with polarization vision techniques. Specularities, occluding contours, and material properties can be readily extracted if the Stokes polarization parameters are available. Astrophysicists employ polarization information to measure the spatial distribution of magnetic fields on the surface of the Sun. In the medical field, analysis of the polarization allows the diagnose of disease in the eyes. The retinae of most insect and certain vertebrate species are sensitive to polarization in their environment, but humans are blind to this property of light. Biologists use polarimeters to investigate behaviors of animals-vis-a-vis polarization-in their natural habitats. In this paper, we first present the basics of polarization sensing and then discuss integrated polarization imaging sensors developed in our laboratory.

Silicon on sapphire CMOS for optoelectronic microsystems

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk silicon CMOS technologies. In the bulk silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of silicon-on-sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues.

Asynchronous sampling of 2D arrays using winner-takes-all arbitration

We describe a novel scheme for asynchronous communication of information out of two dimensional processing arrays. Our architecture employs analog Winner Takes All (WTA) circuits instead of digital binary-tree arbiters found in other designs. A small system that incorporates an array of 9/spl times/12 pixels has been fabricated in a 2/spl mu/, double polysilicon, double metal process. Experimental results verify system functionality with a full-handshaking communication cycle of 3 /spl mu/s. The WTA circuits have been independently tested and their operation verified down to 18 ns.

Multichannel ultrathin silicon-on-sapphire optical interconnects

Multichannel optical interconnects were developed using vertical-cavity surface-emitting laser (VCSEL) arrays and metal-semiconductor-metal photodetector (PD) arrays and driven by complementary metal-oxide-semiconductor circuits that were fabricated using ultrathin silicon-on-sapphire (SOS) technology. Low-threshold oxide-confined top-emitting VCSEL 8/spl times/8 arrays were designed and fabricated with off-site contact bonding pads. The arrays were flip-chip bonded to driver arrays on sapphire substrates and mounted on high-speed printed-circuit boards as optical transmitter arrays. The laser output was transmitted through the transparent sapphire substrate and coupled to MSM PD arrays and the SOS receiver. This optical interconnect system was demonstrated to operate at a data rate of 1.0 Gb/s per channel with a power consumption of 28 mW for each channel including transmitter and receiver.

Mismatch in photodiode and phototransistor arrays

We characterized photodetector mismatch in 2 /spl mu/m and 1.2 /spl mu/m CMOS processes. 32/spl times/32 element photodiode and phototransistor arrays were fabricated in each process, Light response measurements were made using a DC light source and neutral density filters. Dark currents were also measured and characterized. Our measurements reveal less than 2% mismatch for photodiodes over 4 orders of magnitude of intensity, and less than 5% mismatch for phototransistors. The oxide profile above the photodetector array is shown to be responsible for edge-effects.

Asynchronous Communication of 2D Motion Information UsingWinner-Takes-All Arbitration

We describe a system that communicates motion informationcomputed in a 2D photosensitive array using fully arbitered,asynchronous channels. The architecture is neurally inspired,and employs analog winner-takes-all (WTA) circuits, instead ofthe digital binary-tree arbiters found in other designs. We havefabricated a prototype system that incorporates an array of 9×12 pixels in a 2 µm, double-polysilicon,double-metal process. Experimental results verify system functionalitywith a full-handshaking communication cycle of 3 µs.We have tested the WTA circuits independently, and have verifiedtheir operation down to an 18 ns cycle.

A silicon retina for polarization contrast vision

Polarization vision is prevalent among insects, and offers visual capabilities that contribute to object discrimination and homing tasks. We present a CMOS imager that is capable of extracting polarization contrast in a scene. A similar visual modality has been seen in Octopus. The polarimetric vector is a more general descriptor of light than intensity information alone, and it contains physical information about the imaged objects in a scene that traditional intensity based sensors ignore. Polarimeters-devices that measure polarization-are used to extract physical features from an image such as specularities, occluding contours, and material properties. Polarization information is used to perform difficult tasks such as image segmentation and surface reconstruction, object orientation, material classification, atmospheric and solar analysis. The polarization contrast retina is a CMOS sensor/imager that uses a birefringent crystal micropolarizer mounted on the focal plane to sense two orthogonal directions of linear polarization. The CMOS imager uses analog translinear circuitry to compute, in real-time on the focal-plane, polarization contrast: a measure of the orientation and degree of linear polarization in an imaged scene.

A CMOS Neural Interface for a Multichannel Vestibular Prosthesis

We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45±0.06 mA with durations as short as 10 μs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68-130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9-16.7 °/s for the MVP2 and 2.0-14.2 °/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference (t-test, p=0.34), suggesting that the MVP2A achieves performance at least as good as the larger MVP2.

Edge orientation enhancement using optoelectronic VLSI and asynchronous pulse coding

We describe the implementation of one channel of an optoelectronic orientation enhancement algorithm based on a neurally inspired algorithm. An 8/spl times/8 VCSEL (Vertical Cavity Surface Emitting Laser) array, hybridized to CMOS driver circuits, transmits a contrast-enhanced image that would be computed in the early stages of visual processing. A diffractive optical element (DOE) generates a projective field which reinforces pixels of a preferred orientation. A CMOS receiver integrates correlated pulses to produce high output in frequently activated areas. Data from a one channel system shows orientation enhancement.

Contactless fluorescence imaging with a CMOS image sensor

In this work, we utilize a CMOS active pixel sensor in a fluorescence imaging setup. The ability to sense small light intensity changes on top of a large baseline with spatial resolution at the subcellular scale is required in fluorescence imaging. The CMOS imager presented in [1] is perfect for this application with the ability to resolve fine features coupled with high dynamic range. By using a custom imager with a relay lens we are able to realize a dramatic decrease in device size, cost and complexity of the whole system.