Zbigniew Jaworski

Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for a Realistic Circuit Simulation of VLSI Circuits

This paper discusses methodology of statistical simulation of an IC design which includes disturbances described by independent random variables, spatially correlated random disturbances and deterministic process parameters distribution on a wafer. The method of coupling of a process/device simulator with a circuit extractor is proposed. Practical example of an operational amplifier design optimization is presented.

Extension of inductive fault analysis to parametric faults in analog circuits with application to test generation

Parametric fault modeling methodology based on statistical process simulation is proposed. Statistical simulation based on process disturbances allows one to avoid testing for faults which are unlikely to occur. As a result, the number of tests required to verify the circuits performance is reduced. A practical example with results measured on prototype chips is presented.

Fuzzy logic controller for rate-adaptive heart pacemaker

Abstract A family of fuzzy logic controller realization for rate-adaptive cardiac pacemakers has been developed. 1 The implemented algorithm offers good adaptation of the pacing rate to the physiological needs of the patient and easy personalization. However, its usefulness depends on the details of practical implementation such as the necessary hardware resources, programmability, accuracy and power consumption. Several hardware implementations were studied, including software emulation on general purpose low power microprocessors as well as dedicated digital and mixed-mode ASICs, confirming feasibility of practical implementation of the models.

Particularities of cyclic intelligent ADC design, implementation and adjusting

The paper presents the results of design, implementation and adjusting of the CMOS version of the hardware prototype of new ldquointelligentrdquo cyclic analog-to-digit converter (IC ADC). There are presented the concept of intelligent conversion, main principles of practical implementation, main stages and particularities of design and adjusting the IC ADC.

Fuzzy logic-based diagnostic algorithm for implantable cardioverter defibrillators

OBJECTIVE The paper presents a diagnostic algorithm for classifying cardiac tachyarrhythmias for implantable cardioverter defibrillators (ICDs). The main aim was to develop an algorithm that could reduce the rate of occurrence of inappropriate therapies, which are often observed in existing ICDs. To achieve low energy consumption, which is a critical factor for implantable medical devices, very low computational complexity of the algorithm was crucial. The study describes and validates such an algorithm and estimates its clinical value. METHODOLOGY The algorithm was based on the heart rate variability (HRV) analysis. The input data for our algorithm were: RR-interval (I), as extracted from raw intracardiac electrogram (EGM), and in addition two other features of HRV called here onset (ONS) and instability (INST). 6 diagnostic categories were considered: ventricular fibrillation (VF), ventricular tachycardia (VT), sinus tachycardia (ST), detection artifacts and irregularities (including extrasystoles) (DAI), atrial tachyarrhythmias (ATF) and no tachycardia (i.e. normal sinus rhythm) (NT). The initial set of fuzzy rules based on the distributions of I, ONS and INST in the 6 categories was optimized by means of a software tool for automatic rule assessment using simulated annealing. A training data set with 74 EGM recordings was used during optimization, and the algorithm was validated with a validation data set with 58 EGM recordings. Real life recordings stored in defibrillator memories were used. Additionally the algorithm was tested on 2 sets of recordings from the PhysioBank databases: MIT-BIH Arrhythmia Database and MIT-BIH Supraventricular Arrhythmia Database. A custom CMOS integrated circuit implementing the diagnostic algorithm was designed in order to estimate the power consumption. A dedicated Web site, which provides public online access to the algorithm, has been created and is available for testing it. RESULTS The total number of events in our training and validation sets was 132. In total 57 shocks and 28 antitachycardia pacing (ATP) therapies were delivered by ICDs. 25 out of 57 shocks were unjustified: 7 for ST, 12 for DAI, 6 for ATF. Our fuzzy rule-based diagnostic algorithm correctly recognized all episodes of VF and VT, except for one case where VT was recognized as VF. In four cases short lasting, spontaneously ending VT episodes were not detected (in these cases no therapy was needed and they were not detected by ICDs either). In other words, a fuzzy logic algorithm driven ICD would deliver one unjustified shock and deliver correct therapies in all other cases. In the tests, no adjustments of our algorithm to individual patients were needed. The sensitivity and specificity calculated from the results were 100% and 98%, respectively. In 126 ECG recordings from PhysioBank (about 30min each) our algorithm incorrectly detected 4 episodes of VT, which should rather be classified as fast supraventricular tachycardias. The estimated power consumption of the dedicated integrated circuit implementing the algorithm was below 120nW. CONCLUSION The paper presents a fuzzy logic-based control algorithm for ICD. Its main advantages are: simplicity and ability to decrease the rate of occurrence of inappropriate therapies. The algorithm can work in real time (i.e. update the diagnosis after every RR-interval) with very limited computational resources.

Resistive Plate Chamber (RPC) based Muon Trigger System for the CMS experiment – PAttern Comparator ASIC

Abstract The CMS detector will have a dedicated subdetector (RPC chambers) to identify muons, measure their transverse momenta pt, and determine the bunch crossings from which they originate. The trigger algorithm is based on muon track search and classification in raw data from the RPC chambers grouped in the four muon stations in the CMS magnet yoke. The PAttern Comparator (PCA) ASIC will search for tracks of muons and measure their momenta. The idea of PAC and its first prototype implementation are shown here.

VLSI implementations of fuzzy logic controllers for rate-adaptive pacemakers

An efficient fuzzy logic-based control algorithm for rate-adaptive cardiac pacemakers has been developed recently. This algorithm offers good adaptation of the pacing rate to the physiological needs of the patient and easy personalization. However, its usefulness depends on the details of practical implementation such as the necessary hardware resources, programmability, accuracy and power consumption. This work presents a study of several possible implementations including ASIC chips designed specifically for this application as used as implementations in commercially available microprocessors.

Verilog HDL model based thermometer-to-binary encoder with bubble error correction

This paper compares several approaches to come up with the Verilog HDL model of the thermometer-to-binary encoder with bubble error correction. It has been demonstrated that implementations of different ideas to correct bubble errors yield circuits whose parameters tremendously vary in delay, area and power consumption. The shortest delay is achieved for the design synthesized from the model which mimics a human reading temperature on classic liquid-in-glass thermometer.

Architecture of a testable analog fuzzy logic controller

The authors discuss problems of testability of analog fuzzy logic controllers implemented as VLSI chips. Enhancements to standard architecture of fuzzy logic controllers which facilitate testing are proposed. To improve controllability and observability of internal nodes, analog switching blocks are introduced together with some additional circuitry. These blocks allow one to test each basic cell of a fuzzy logic controller (e.g., membership function cell, MINIMAX cell, etc.) separately. The analog switching blocks do not contribute to the power consumption in a working chip end therefore can be used in low-power analog fuzzy logic controllers.

Robustness of digital approach to mismatch compensation in analog circuits realized in nanometer technologies

In this papers, a fully differential operational transconductance amplifier (OTA) implemented in 65 nm CMOS technology is analyzed to determine which component of the calibration circuitry is most susceptible to manufacturing process disturbances and thus impairs robustness of the calibration methodology. The average offset voltage of the OTA can be significantly reduced. It has been shown that effectiveness of the calibration methodology is limited by the offset voltage of the comparator that calculates sign of the OTA offset voltage.