Andrzej Wielgus

Fuzzy logic controller for rate-adaptive heart pacemaker

Abstract A family of fuzzy logic controller realization for rate-adaptive cardiac pacemakers has been developed. 1 The implemented algorithm offers good adaptation of the pacing rate to the physiological needs of the patient and easy personalization. However, its usefulness depends on the details of practical implementation such as the necessary hardware resources, programmability, accuracy and power consumption. Several hardware implementations were studied, including software emulation on general purpose low power microprocessors as well as dedicated digital and mixed-mode ASICs, confirming feasibility of practical implementation of the models.

VLSI implementations of fuzzy logic controllers for rate-adaptive pacemakers

An efficient fuzzy logic-based control algorithm for rate-adaptive cardiac pacemakers has been developed recently. This algorithm offers good adaptation of the pacing rate to the physiological needs of the patient and easy personalization. However, its usefulness depends on the details of practical implementation such as the necessary hardware resources, programmability, accuracy and power consumption. This work presents a study of several possible implementations including ASIC chips designed specifically for this application as used as implementations in commercially available microprocessors.

Implementation of the ADELITE Microcontroller for Biomedical Applications

Recently, we are witnessing a rapid development in many fields of science, including medicine and healthcare. One of the visible results of such progress is an increasing average length of human life and the process of population aging. Advancements in sensor technology and wireless communication contributed to the development of the out-of-hospital health-monitoring concept [1]. One of its main advantages is the opportunity to provide remote healthcare, which enables extended independent living at home and improvement of quality of live. This paper presents the ADELITE micro controller for biomedical applications. While developed biomedical analog front-end of ADELITE micro controller is currently under measurements, results presented in the paper refer to the first implementation of the digital part of the developed micro controller. The long term target of the design is a full system-on-chip implementation. The presented prototype of ADELITE micro controller was fabricated with UMC CMOS 130 nm technology. The design occupies the area of 1.5 mm2 and consumes only 100 μA/MHz. The ADELITE processing power is 0.95 DMIPS/MHz and 1.89 Core Mark/MHz with 16 MHz of clock frequency.

BioSoC: Highly integrated System-on-Chip for health monitoring

The BioSoC is a highly integrated SoC that consists of analog front-ends, analog to digital converters and a 32-bit microcontroller - Adelite. The designed IC allows for dynamic acquisition and processing of the most important human physiological parameters. The provided analog interfaces to external electrodes and sensors allow measurement of electrocardiograms (ECG), electromyograms (EMG), skin temperature and resistance, and respiration rate (RR). After analog processing signals are sampled and digitized in analog-to-digital converters they can be further processed in a 32-bit microcontroller Adelite. The clock frequency of the microprocessor core is configurable from 32 kHz up to 16 MHz. The microcontroller is equipped with many digital interfaces and peripherals, such as 2×UART and 2×SPI with DMA channels, 16 GPIOs and 5 timers along with RTC. The BioSoC makes it possible to build highly integrated devices with rich functionalities in the area of telemedicine that respond to the growing demand for portable health monitoring. The BioSoC was designed and fabricated in UMC CMOS 130 nm technology process and occupies the area of 25mm2.

Algorithms of multilevel synthesis of fuzzy functions

This paper presents a new method of multilevel synthesis of fuzzy functions obtained from the behavioural description of a fuzzy system being implemented. New methodology relies on representing the fuzzy functions by logic expressions in the form of polynomials, which can be transformed according to the rules of polynomial algebra. The transformations are based on the extraction of common subexpressions, which is supported by a new algorithm of fuzzy division. As a result of the synthesis, the minimised multilevel structure of the fuzzy cells is obtained.

Resistive shorts characterization in CMOS standard cells for test pattern generation

This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. Resistance of a short defect is taken into account while considering faulty behavior caused by this defect and finding the test vectors that detect this fault. Finally, all of found vectors are validated to check their effectiveness in fault covering and the optimal test sequence for all detectable faults is constructed. Experimental results for cells from industrial standard cell library are presented.

Characterization of CMOS sequential standard cells for defect based voltage testing

This paper presents a new characterization methodology of CMOS sequential standard cells for defect based voltage testing. It allows to estimate the probabilities of physical defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults. Finally, all of found sequences are validated to check their effectiveness in fault covering and the optimal complex test sequence for all detectable faults is constructed. Experimental results for sequential cells from industrial standard cell library are presented.

Digital Implementation of a Programmable Reconfigurable Fuzzy Automaton for Control Applications

This paper presents the design of a digital CMOS integrated circuit implementing fuzzy finite state automaton as a fuzzy logic controller. The parameterised VHDL model allows to synthesise the circuit of the required size for a particular application. Moreover, on-chip programming and reconfiguration of the automaton is performed.

CMOS standard cells characterization for open defects for test pattern generation

This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. It allows to estimate the probabilities of physical open defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults. Finally, the minimal set of test sequences is selected to cover all detectable faults and the optimal complex test sequence is constructed. Experimental results for cells from industrial standard cell library are presented as well.

Heuristic algorithm of two-level minimization of fuzzy logic functions

Two-level minimization is an important step in multilevel synthesis of fuzzy logic functions. The paper discusses some methods of both exact and approximate minimization. A new heuristic algorithm, based on the fuzzy consensus method, is proposed. Example results of minimization are reported and compared with the results of the exact methods.