Zdeněk Kotásek

Automated Functional Verification of Application Specific Instruction-set Processors

Nowadays highly competitive market of consumer electronics is very sensitive to the time it takes to introduce a new product. However, the ever-growing complexity of application specific instruction-set processors (ASIPs) which are inseparable parts of nowadays complex embedded systems makes this task even more challenging. In ASIPs, it is necessary to test and verify significantly bigger portion of logic, tricky timing behaviour or specific corner cases in a defined time schedule. As a consequence, the gap between the proposed verification plan and the quality of verification tasks is widening due to this time restriction. One way how to solve this issue is using faster, efficient and cost-effective methods of verification. The aim of this paper is to introduce an automated generation of SystemVerilog verification environments (testbenches) for verification of ASIPs. Results show that our approach reduces the time and effort needed for implementation of testbenches significantly and is robust enough to detect also well-hidden bugs.

FITTest BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties

In the paper, the FITTest_BENCH06 set of synthetic benchmark circuits is presented for the evaluation of diagnostic methods and tools. The structure of benchmark circuits together with their diagnostic properties is described. The set consists of 31 circuits at various levels of complexity (2000, 10000, 28000, 100000, 150000 and 300000 gates). Four circuits with different diagnostic properties are available for each level of circuit complexity (fault coverage is approx. 0%, 33%, 66% and 100%). The benchmark circuits are available both at the register transfer level and the gate level. In addition to the benchmark set, a method is described that was used to develop benchmark circuits with required complexity and diagnostic properties

Analysis and comparison of functional verification and ATPG for testing design reliability

As the complexity of current hardware systems rises, it is challenging to harden these systems against faults and to complete their verification and manufacturing test. Not only that verification and testing take a considerable amount of time but the number of design errors, faults and manufacturing defects increases with the rising complexity as well. In this paper we performed a detailed analysis of two approaches devoted to generation of input test vectors with respect to detection of stuck-at faults: the first one is based on classical Automatic Test Pattern Generation, the second one on Constrained-random Stimulus Generation. We evaluated their qualities as well as their drawbacks and introduced ideas about their combination in order to create a new promising approach for testing reliable systems.

Decreasing test time by scan chain reorganization

In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.

Partial Scan Methodologies-A Survey

Abstract In the paper the survey of partial scan methodologies is presented. Existing approaches for selecting FFs for partial scan can be classified as testability analysis based, test generation based and structural analysis based. In the paper, the results of our research activities are described as well. The methodology is based on such concepts as Test Input Register (TIR), Test Driver (TDR), Test Receiver (TRV), Test Output Register (TOR) and Test Transmitter (TTR).